Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs

2.5 Summary

Typically used MOSFET parameter extraction methods have been presented in this chapter, with focus on large area transistor BTI characterization. Due to the large density of fast traps in SiC MOSFETs, compared to their Si counterparts, it is essential to record the full device history of the DUT starting from its pristine state. If the discussed preconditioning schemes are applied, they also need to be considered within a transient simulation. Gate stack parameter extraction from CV curves and their correct reproduction by simulation require fully self-consistent computational schemes, which limits their usability for ideal device electrostatic calibration, compared to Si-based MOSFETs, and one needs to fall back to the exact knowledge of doping profiles and gate oxide thickness for simulating SiC MOSFETs.