Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs

Chapter 6 Summary and Outlook

A synopsis of the results of this thesis concludes with the advances for the research field presented in the summary of this chapter. Based on the used methods and obtained results, suggestions for future extensions of this work related to unresolved challenges of characterizing and modeling SiC MOSFET reliability are finally discussed.

6.1 Summary

For the first time, a large set of data characterizing BTI in different SiC based MOSFETs has been reproduced by device level simulation of threshold voltage shifts. For this, a two-state non-radiative multi-phonon model has been employed to accurately describe the kinetics of charge capture and emission at pre-existing structural defects. This model as implemented into the simulation framework Comphy solely relies on physical material parameters to calculate the ideal MOS electrostatics. To extract defect parameters from the extensive data set, with many potential defect distributions present at a large number of total defects, a novel ESiD algorithm has been used. This method has enabled the physical parametrization of the NMP model, which allowed to obtain similarities of parameter distributions for electron traps among the investigated lateral channel SiC MOS devices and comparable bulk oxide defects as extracted in Si based MOSFETs employing the same native oxide, i.e. SiO₂. Furthermore, these electron traps were demonstrated to be present in DMOS technologies of different manufacturers and generations with varying densities. However, large differences in the hole trap densities amongst the technologies has been obtained. The calibration of the reliability framework Comphy further enabled the extrapolation of ∆V_th/∆R_on of the DMOS technologies beyond typical experimental time-scales for operation relevant AC gate drive signals, rendering bi-polar gate drive signals with small negative off bias as the most stable operation condition.

In the second part of the work, a novel TAT modeling approach has been developed, including both defect to reservoir and defect to defect charge transfer reactions by employing a reduced NMP parametrization. These multi-TAT transitions have been shown to presumably play a negligible role in most MOS gate stacks, by an evaluation following the implementation of the model in Comphy. Quite to the contrary, TAT currents via single defects have been accurately reproduced in technologies employing SiC/SiO₂ and ZrO₂ based capacitors. The defect parameters used in both technologies excellently fit those obtained for polarons with DFT. This renders polarons a likely charge transition center to enable TAT currents in binary oxides quite in general.