A.3.1 System Modeling

A simple model of a digital synchronous system is shown in Fig. A.16. Several blocks of combinatorial logic are embedded between latches or registers, which are controlled by a common clock signal $\Phi$. The digital functionality of such a system can be described in terms of a finite state machine. The electrical properties such as speed and power consumption can be modeled by a few parameters together with gate specific electrical data. The set of parameters is explained in the following paragraphs, while the equations for power consumption, delay times, etc. are given in the respective sections of2 and  Chapter 3.

The average number of inputs of a gate and the number of unit inputs connected to a gate output is the average fan-in/fan-out , which affects the gate delay . The average length can be computed using Rent's rule which takes a number of further system and technology parameters [5]. For this work an average of 200 was assumed, which is a typical value for microprocessors. The interconnect capacitance per length is in the range of $\rm0.2fF/\mu m$ for most technologies.

The ``distance'', i.e., the number of gates in a signal path between two registers (including one register) is the so-called logic depth . It determines the maximum clock frequency $\ensuremath{f_{\mathit{c,max}}}\xspace \approx 1/(\ensuremath{t_{\mathit{g}}}\xspace \ensuremath{{\mathit{ld}}}\xspace )$ (cf. Section 3.1.6) and also the area and power efficiency of the system (if the logic depth is too small more space and power will be used up by the registers). Typical values are 5...15. The probability for a circuit node to change its state during a clock cycle is the so-called activity ratio . The activity ratio of microprocessors is typically 0.1...0.3. The value of for memories is in general much smaller and depends largely on the access statistics. The percentage at which a system is in standby mode is the standby ratio . For many analyses it is applicable to use an effective activity ratio $\ensuremath{{\mathit{ar_{\mathit{eff}}}}}\xspace = \ensuremath{{\mathit{ar}}}\xspace (1-\ensuremath{{\mathit{sr}}}\xspace )$. The percentage of effective drain leakage $\ensuremath{I_{\mathit{off,eff}}}\xspace /\ensuremath{I_{\mathit{off}}}\xspace$ is the leakage ratio . For example, N transistors in a product term have a leakage ratio of $\le 1/N$. This parameter provides also a possibility to account for power-down operation in standby modes. Note that the latter two parameters, and , are not commonly used. For this work $\ensuremath{{\mathit{sr}}}\xspace = 1$ and $\ensuremath{{\mathit{lr}}}\xspace = 1$ is assumed, unless otherwise noted.

Figure A.16: Digital VLSI system model

A few words of caution on the simplicity and scope of this rather simple model should be mentioned: A system which can be described in terms of the aforementioned parameters with spatially constant values is called homogeneous. In reality, however, digital systems consist of several components, each of which has quite different properties. For example, in a typical microprocessor, the activity ratio is 1.0 for the clock drivers, 0.3 for the processor core components, and much less for the cache memory (depending on its size). Furthermore, when the model is used to accurately predict, e.g., the power consumption or the performance of a system constant values for some of the parameters, especially, and , are no longer sufficient. For this purpose, a variety of statistical modeling methods have been developed [51,20,21,85]. For the purpose of this work, i.e., the assessment of technology and device design options, however, a simple homogeneous-system model using the parameters listed above is sufficient. Furthermore, all relevant methods laid down in Section 3.3 can be interfaced to non-homogeneous or statistical system models as well.