Predictive and Efficient Modeling of Hot Carrier Degradation with Drift-Diffusion Based Carrier Transport Models
8.2 Application of the Extended HCD Model to Scaled Devices
Figures 8.3 8.5 and 8.8 show very good agreement between the DFs simulated
with our drift-diffusion based approach and with ViennaSHE for all combinations of
and
in 65
nm nMOS as well as for 150 and 300
nm nMOSFETs. Incorporation of the knee energies allow for an accurate representation of the high-energy tails and in particular the effect of EES. The values of
calculated with the analytical model are almost the same as those
obtained from ViennaSHE for all the devices and stress conditions, see Figures 8.6, 8.7 and 8.9, thereby suggesting the validity of the rate balance method.
Figure 8.11: Same as Figure 8.10 but for 300 nm nMOSFET.
After the second knee energy the analytic DFs show a visible error, especially for the 65 and 150 nm cases. However, the concentrations at these energies are quite low and do not affect hot-carrier degradation.
The carrier DFs obtained from ViennaSHE and the analytical approach are used with
our HCD model [13, 24] to calculate the interface state density ( ) profiles. The
profiles obtained from our physics-based HCD model for the three devices are shown in Figures 8.10 and 8.11. Figures 8.10 and 8.11 suggest that both SHE- and DD-based versions of the model for stress times of 1
s and 4
ks give similar results. These
profiles are then used to simulate the characteristics of the degraded device.
To validate the model against experimental data, the HCD data acquired on SiON nMOSFETs with a gate length of 65 nm is used. These 65
nm devices were stressed under three different stress conditions, i.e.
=
= 1.8
V and 2.0
V at room temperature for
8
ks. The relative changes in linear drain current
were recorded as a function of
stress time. A slight discrepancy in profiles and DFs visible at
-5
nm in the scattering dominated region does not translate into a model error. Figure 8.12 shows that the simulated
traces are almost identical and are in very good agreement with experimental data. As for the 150
nm transistor, Figure 8.13, there is a slight discrepancy in the results obtained with the DD-based and the full version of the model, which
arises from a mismatch in the DFs observed at high energies. Finally, in the 300
nm nMOSFET, the DFs,
acquired from the two methods match very well.
As can be understood from the schematic Figure 8.2, the DF should change its shape at a certain position in the device, say . The value of
is an important parameter of
the model and therefore it is worth to study the model sensitivity to a change of to check the robustness of the model. The value of the coordinate
is varied and the corresponding
traces are determined. Figures 8.14 and 8.15 summarize
traces obtained with modified
values of
0.1
. In all three devices the
dependencies simulated for
0.1
show that HCD is underestimated at short times and almost by the same amount for longer stresses. HCD at short stress times is determined by the damage produced near the drain, i.e. by the drain DFs [24]. If we increase the
value the change of the DF shape shown in Figure 8.2 occurs closer to the drain. Thus, DFs calculated for the segment of
have lower populated high-energy tails and the damage near the drain is underestimated, thereby resulting in underestimated HCD at short stress times. The opposite trend is visible if
dependencies are calculated for
0.1
.
Figure 8.15: Same as Figure 8.14but for 300 nm device.