Predictive and Efficient Modeling of Hot Carrier Degradation with Drift-Diffusion Based Carrier Transport Models

Chapter 2 Hot-Carrier Degradation 2

The semiconductor device fabrication process requires the growth of a dielectric, such as amorphous silicon gate oxide ( $\mathrm {SiO_{2}}$ ) or high-k dielectric such as $\mathrm {HfO_{2}}$ , on the crystalline silicon bulk/substrate ( $\mathrm {Si}$ ). The lattice mismatch at the interface of the dielectric and the substrate induces mechanical stress, leaving some of the $\mathrm {Si}$ atoms unsaturated. In other words, some $\mathrm {Si}$ atoms do not form four bonds with neighboring atoms to complete the octet. As a result, they carry up to two unpaired electrons, thereby creating two trap levels in the $\mathrm {Si}$ bandgap. This corresponds to electrically active Si dangling bonds which are visible in paramagnetic spin-resonance experiments [112, 113]. A large number of the unsaturated $\mathrm {Si}$ bonds are passivated with $\mathrm {H}$ gas during post-grow anneal. This creates electrically inactive Si-H bonds at the interface and shifts the corresponding energy levels out of the $\mathrm {Si}$ bandgap [114, 115]. However, during stress/operation of the device at high electric fields, carriers with high energies (as shown in Figure 1.4) can break the Si-H bonds, thereby creating interface traps. These defects at the interface are characterized by a density called the interface state density $N_{\mathrm {it}}$ (cm^-2), which represents the number of interface traps per unit area or $D_{\mathrm {it}}$ (cm^-2 eV^-1), the number of interface traps per unit area distributed across the energy bandgap [39]. The electrically active interface defects lead to

a threshold voltage shift ( $\Delta V_{\mathrm {t}}$ ) and the degradation of the drain current ( $\Delta I_{\mathrm {d,lin}}$ , $\Delta I_{\mathrm {d,sat}}$ ), thus, limiting the lifetime of the device. The traps also contribute to the leakage current and low frequency noise, thereby further disrupting the device functionality.

The charge stored in the traps depends on their position with respect to the Fermi level and thus on the bulk material, bias and temperature conditions, see Figure 2.1. The states between the intrinsic level ( $E_{\mathrm {i}}$ ) and the valence band ( $E_{\mathrm {V}}$ ) are filled with electrons and are donor-like as in a p-type substrate. On the other hand, the states between conduction band edge ( $E_{\mathrm {C}}$ ) and $E_{\mathrm {i}}$ are acceptor-like as in a n-type substrate [116]. For instance, in the case of flatband conditions, if the Fermi level ( $E_{\mathrm {F}}$ ) is between E (math image) and $E_{\mathrm {i}}$ , the traps below $E_{\mathrm {F}}$ accept an electron to complete the octet and thus are negatively charged similar to occupied acceptors. Other states carry one unpaired electron and are neutral. On the other hand, if the Fermi level shifts below $E_{\mathrm {i}}$ , the traps between $E_{\mathrm {i}}$ and $E_{\mathrm {F}}$ loose an electron and are positively charged (unoccupied donors) while other states stay neutral being populated by electrons [39].

To sum up, interface traps are charged when they are donor-like and donate electrons (positively charged traps) or if they are acceptors and accept electrons (negatively charged traps). Otherwise the traps are neutral and benign. The traps that are charged create fields which interfere with the electrical properties of the devices. As the trap density increases during the course of device operation, the number of charged traps also increase ultimately leading to the device breakdown.

2.1 Measurement Techniques

Since success of a technology node depends on the quality of the material and interface, determining the spatial distribution of the defects is vital.

Modeling a degradation phenomenon in semiconductor devices to evaluate their performance and lifetime requires the quality of the interface to be precisely characterized. Several signatures of the interfacial Si-H bond can help determine the interface state density. These include the $\mathrm {SiO_{2}}$ / $\mathrm {Si}$ interface charges through their distortion of the electrostatics, drain-source currents originating due to interface trap states and hopping of the carriers, and the recombination current. Several techniques are used for spatially locating the interface states and tracking their evolution during stress conditions. [117, 118, 119, 120, 121]. Some widely used methods, namely the charge pumping, capacitance-voltage characteristics, and the conductance technique are explained below.

2.1.1 Charge Pumping

When periodic pulses are applied to the gate of a metal-oxide-semiconductor transistor, the recombination of carriers trapped by the interface states present in the

channel region of the device produces the charge pumping current [118, 119]. A simple setup for the charge pumping method is shown in Figure 2.2. The gate is pulsed between accumulation and inversion conditions with the reverse biased substrate-source and substrate-drain p-n junctions. The charge pumping current produced from recombination is measured at the substrate. Alternatively, the current can be measured at the source/drain connection or at source and drain separately.

The recombination takes place in the $L_{\mathrm {eff}}$ region, see Figure 2.2. Thus, the experimental charge pumping current is the average recombination current originating from the $L_{\mathrm {eff}}$ region in the channel.

The generation of charge pumping current is described in Figure 2.3. When the gate voltage approaches inversion, the interface is flooded, up to a certain distance, with minority carriers from the drain and source regions. Considering the drain side in Figure 2.2, the interface is flooded with minority carriers up to some distance $A$ (measured from the drain) during inversion. The majority carriers are swept into the substrate. Consequently, the interface states in this region capture minority carriers and are devoid of majority carriers. When the gate voltage approaches accumulation, the minority carriers travel back to the drain and majority carriers move from the substrate to the interface and reach point $B$ (measured from drain) with $B<A$ . In the region $L_{\mathrm {eff}}/2$ ( $A-B$ ), recombination takes place, which leads to the charge pumping current. Outside this region, the supply of either electrons or holes is insufficient for recombination to take place.

It is worth mentioning that not all the electrons/holes captured by interface states in the $L_{\mathrm {eff}}$ region contribute to the recombination current [118, 119]. This is explained in the following example of constant high level charge pumping in a pMOSFET, Figure 2.4. During accumulation (positive $V_{\mathrm {gl}}$ ), most of the interface states are filled with electrons up to the accumulation energy level $E_{\mathrm {acc}}$ . As the interface moves from accumulation into weak inversion (from flatband voltage $V_{\mathrm {fb}}$ to threshold voltage $V\mathrm {_{th}}$ ) via depletion, electrons are emitted from the traps back into the substrate due to thermal emission.

When the threshold voltage is reached, all the states with energy greater than $E_{\mathrm {em,e}}$ are devoid of electrons. As the interface turns into inversion mode (negative $V_{\mathrm {gh}}$ ), holes flood in from the source and drain leading to emptying of traps via hole capture up to an energy level $E_{\mathrm {inv}}$ . As the gate voltage increases back towards accumulation, holes move back to source and drain and the traps below a certain energy level, $E_{\mathrm {em,h}}$ , are filled with electrons via hole emission. The interface states above this energy level are filled by electrons captured during accumulation. Thus, only the fast traps between $E_{\mathrm {em,e}}$ and $E_{\mathrm {em,h}}$ in the Si bandgap contribute to the charge pumping current. These energy levels can be calculated as [118]:

$(2.1–2.2) \{begin}{align} E_{\mathrm {em,e}}= & E_{\mathrm {i}}-k_{\mathrm {B}}T\ln \left (v_{\mathrm {th}}\sigma _{\mathrm {e}}n_{\mathrm {i}}t_{\mathrm {em,e}}+\exp \left (\frac {E_{\mathrm {i}}-E_{\mathrm {F,inv}}}{k_{\mathrm {B}}T}\right )\right )\label {eq:Energy-level-r}\\ = & E_{\mathrm {i}}-k_{\mathrm {B}}T\ln \left (v_{\mathrm {th}}\sigma _{\mathrm {e}}n_{\mathrm {i}}\left |\frac {V\mathrm {_{th}}-V\mathrm {_{fb}}}{\Delta V_{\mathrm {g}}}\right |t_{\mathrm {r}}\right ),\nonumber \\ E_{\mathrm {em,h}}= & E_{\mathrm {i}}+k_{\mathrm {B}}T\ln \left (v_{\mathrm {th}}\sigma _{\mathrm {h}}n_{\mathrm {i}}t_{\mathrm {em,h}}+\exp \left (\frac {E_{\mathrm {F,acc}}-E_{\mathrm {i}}}{k_{\mathrm {B}}T}\right )\right )\label {eq:Energy level-f}\\ = & E_{\mathrm {i}}+k_{\mathrm {B}}T\ln \left (v_{\mathrm {th}}\sigma _{\mathrm {e}}n_{\mathrm {i}}\left |\frac {V\mathrm {_{th}}-V\mathrm {_{fb}}}{\Delta V_{\mathrm {g}}}\right |t_{\mathrm {f}}\right ),\nonumber \{end}{align}$

where, $E_{\mathrm {i}}$ is the intrinsic energy level, $E\mathrm {_{F,inv}}$ and $E\mathrm {_{F,acc}}$ are Fermi energies in inversion and accumulation, $v_{\mathrm {th}}$ is the thermal velocity, $\mathrm {\sigma }_{\mathrm {e}/\mathrm {h}}$ the capture cross section of the traps, and $n_{\mathrm {i}}$ the intrinsic carrier concentration. Outside this band, thermal emission is the most prominent source of de-trapping.

Once the charge pumping currents are measured, $N_{\mathrm {it}}$ can be extracted using the steps described below. As an example, sample measurement data for a 65 $\,$ nm nMOS transistor at temperature of 25 $\,$ ^oC is used. For this temperature, the device was stressed for eight different times and the charge pumping current was measured using the constant base level and fixed high level techniques.

As a first step in the $N_{\mathrm {it}}$ extraction procedure, it is important to determine whether the initial interface state distribution is uniform, non-uniform or locally uniform.

The charge pumping current measurements for unstressed devices created using the same process but having different gate lengths can provide information on the nature of the $N_{\mathrm {it}}$ distribution. The maximum charge pumping current versus the gate length curve for 65 $\,$ nm nMOS devices used in this example and longer gate length transistors created on the same process are shown in Figure 2.5. Figure 2.5 suggests that the interface state profile for a fresh transistor considered here is non-uniform as the increase in the interface state density is not proportional to the increase in the channel length [122]. However, the pre-stressed $N_{\mathrm {it}}(x)$ profiles are significant only when HCD is not very strong, i.e., for low stress times and biases. Due to the high interface state density after severe stresses, the contribution of the pre-stress $N_{\mathrm {it}}(x)$ profile to the total interface state density becomes negligible.

Second, the local threshold and flatband voltages are calculated for the unstressed device, see Figure 2.6. For an nMOS device, the local threshold voltage at a certain coordinate of the interface is defined as the gate voltage at which the traps can capture the minority carriers during inversion. On the other hand, the local flatband voltage at a certain coordinate of the interface is defined as the gate voltage at which the traps can capture the majority carriers during accumulation [123]. Hence, these voltages are derived using the dynamics of the capture and emission process at the interface. For the sample device, our device and circuit simulator Minimos-NT [124, 125] was used to obtain the threshold and flatband voltages. Minimos-NT employs a comprehensive set of physical models to provide steady-state, transient, and small-signal analysis of the devices. The required electron/hole concentration for the interface states to capture electrons/holes can be estimated by:

$(2.3) \begin{equation} n_{\mathrm {e/h}}=\frac {1}{v_{\mathrm {th}}\sigma _{\mathrm {e/h}}\tau _{\mathrm {e/h}}},\label {eq:Vth/fb} \end{equation}$

where $v_{\mathrm {th}}$ is the thermal carrier velocity, $\tau _{\mathrm {e/h}}$ the time constant for electron/hole trapping, and $\sigma _{\mathrm {e/h}}$ the capture cross section for electrons/holes.

Once the threshold voltage profile is obtained, the interface state profiles can be deduced using the expression:

$(2.4) \begin{equation} I_{\mathrm {CP}}=\frac {qW}{T_{\mathrm {P}}}\int _{L_{\mathrm {eff}}}N_{\mathrm {it}}(x)\cdot \mathrm {d}x\label {eq:Icp} \end{equation}$

where $I_{\mathrm {CP}}$ is the time averaged recombination (charge pumping) current, $W$ the width of the interface, and $T_{\mathrm {P}}$ the time period. Through this method, the $N_{\mathrm {it}}(x)$ profiles over a certain distance $L_{\mathrm {eff}}$ can be extracted as already discussed. So for Equation 2.4, the $I_{\mathrm {CP}}$ corresponding to the maximum $L_{\mathrm {eff}}$ / $V_{\mathrm {gh}}$ is used to obtain the $N_{\mathrm {it}}$ over a maximum distance along the interface. Calculating $N_{\mathrm {it}}(x)$ from equation Equation 2.4 proceeds by differentiating the equation on both sides. Thus,

$(2.5) \begin{equation} \frac {\mathrm {d}I_{\mathrm {CP}}}{dx}=\frac {qW}{T_{\mathrm {P}}}N_{\mathrm {it}}(x), \end{equation}$

rewritten as

$(2.6) \begin{equation} \frac {\mathrm {d}I_{\mathrm {CP}}}{\mathrm {d}V_{\mathrm {gh}}}\frac {\mathrm {d}V_{\mathrm {gh}}}{\mathrm {d}x}=\frac {qW}{T_{\mathrm {P}}}N_{\mathrm {it}}(x),\label {eq:Icp-diff} \end{equation}$

$(2.7) \begin{equation} \frac {\mathrm {d}I_{\mathrm {CP}}}{\mathrm {d}V_{\mathrm {gh}}}\frac {\mathrm {d}V_{\mathrm {th}}}{\mathrm {d}x}=\frac {qW}{T_{\mathrm {P}}}N_{\mathrm {it}}(x). \end{equation}$

Here $\mathrm {d}V_{\mathrm {th}}/\mathrm {d}x$ can be considered similar to $\mathrm {d}V_{\mathrm {gh}}/\mathrm {d}x$ as the condition for the threshold voltage. In Equation 2.3, the threshold voltage is reached at $V_{\mathrm {gh}}$ .

The interface state profiles obtained using this procedure (Equation 2.6) for different stress times are shown in Figure 2.7. The extracted $N_{\mathrm {it}}(x)$ profiles were used to simulate a degraded device and calculate the charge pumping currents in Minimos-NT. The comparison of charge pumping currents obtained from simulation with those from experiments are shown in Figure 2.8 for several stress conditions.

2.1.2 Capacitance-Voltage Characteristics

The Capacitance-Voltage (CV) method is another widely used technique to evaluate new processes, materials, and devices [126, 120]. The measurement setup is shown in Figure 2.9. In this method, the interface is swept through different regimes, i.e., accumulation, depletion and inversion, successively and the small signal capacitance is measured. In the accumulation regime, there are a large number of majority carriers at the interface. During depletion, the majority carriers move inside the bulk and only fixed charges remain at the surface which build up the depletion layer. This results in a decrease of the total capacitance. When the semiconductor-insulator interface reaches the inversion mode, the minority carriers populate the surface and balance the gate charge. The total capacitance of the device is a combination of the depletion layer and inversion layer capacitance.

The total space charge density can be expressed as $Q_{\mathrm {SC}}=Q_{\mathrm {d}}+Q_{\mathrm {n}}$ , where $Q_{\mathrm {d}}$ and $Q_{\mathrm {n}}$ are the deletion and inversion layer charge density, respectively [120]. An increase in the interface trap density $\ensuremath {N_{\textrm {it}}}$ is followed by a deformation of the characteristics as the traps can dynamically be charged and discharged, while the fixed oxide charges shift the flat-band voltage. Therefore, the capacitance ( $C$ ) is calculated as:

$(2.8) \begin{equation} C=\frac {\varDelta Q_{\mathrm {it}}+\varDelta Q_{\mathrm {OX}}}{\varDelta V_{\mathrm {th}}}. \end{equation}$

where $Q_{\mathrm {it}}$ is the interface charge density and $Q_{\mathrm {OX}}$ the oxide charge density.

The frequency of the signal applied is very important to consider the contribution due to different regimes. For example, in a MOSCAP, if the signal has a high frequency, only the majority carrier response can be measured as the recombination-generation rates of the minority carriers cannot keep up with small signal variations at high frequencies. In the high frequency limit, the inversion layer charges cannot follow the AC signal. In this regime, the capacitance of the device will be determined by the depletion layer charge density alone [120]:

$(2.9) \begin{equation} C=\frac {q\epsilon _{\mathrm {Si}}N_{\mathrm {A}}}{2\phi _{\mathrm {S}}}\frac {\mathrm {d}\phi _{\mathrm {S}}}{\mathrm {d}t}.\label {eq:9} \end{equation}$

This capacitance calculated from Equation 2.9, using the doping concentration ( $N_{\mathrm {A}}$ ), surface potential ( $\phi _{\mathrm {S}}$ ), and permittivity of silicon ( $\epsilon _{\mathrm {Si}}$ ), is used to evaluate the density of charges stored in interface traps. The interface charge density enters Equation 2.9 via the rate of change of the surface potential $\mathrm {d}\phi _{\mathrm {S}}/\mathrm {d}t$ calculated from $E_{\mathrm {g}}/q+\chi -\phi _{\mathrm {S}}-v_{\mathrm {n}}+V=-\frac {\delta }{\epsilon _{\mathrm {i}}}\left [Q_{\mathrm {d}}+Q_{\mathrm {n}}+Q_{\mathrm {it}}+qN_{\mathrm {f}}\right ]$ , where $E_{\mathrm {g}}$ is the band gap, $\chi$ the electron affinity, $v_{\mathrm {n}}$ the carrier velocity, $V$ the applied bias, $Q_{\mathrm {it}}$ the interface charge density, and $N_{\mathrm {f}}$ the fixed charge density [120].

2.1.3 Conductance method

The conductance method is one the most sensitive methods to determine the interface trap density. This method depends on the analysis of the change in the charge state of the traps when a small AC voltage is superimposed on the DC gate bias. The modulated signal causes the position of the Fermi level to change with respect to the position of the interface states in energy. Thus, the occupancy of the interface states changes, leading to charge release which can be measured as a parallel conductance $G$ . This conductance is measured as a function of frequency $\omega$ . The conductance due to interface traps $G_{\mathrm {it}}$ is calculated using the measured capacitance $C$ and conductance $G$ as:

$(2.10) \begin{equation} \frac {G_{\mathrm {it}}}{\omega }=\frac {\omega ^{2}C_{\mathrm {ox}}^{2}G}{G^{2}+\omega ^{2}(C_{\mathrm {ox}}-C)^{2}}, \end{equation}$

where $C_{\mathrm {ox}}$ is the oxide capacitance and $\omega$ is the angular frequency. The angular frequency $\omega$ is related to the characteristic trap response time $\tau =\exp \left [\Delta E/k_{\mathrm {B}}T\right ]/\sigma v_{\mathrm {th}}D_{\mathrm {dos}}=2\pi /\omega$ with $\sigma$ , $v_{\mathrm {th}}$ , $D_{\mathrm {dos}}$ being the trap capture cross section, carrier thermal energy, and density of states, respectively [127]. A plot of the normalized interface trap conductance $G_{\mathrm {it}}/\omega$ versus frequency has a maximum value corresponding to a peak frequency $f_{\mathrm {p}}$ , implying maximum change in interface state occupancy which occurs when the interface traps are in resonance with the applied ac signal.

To calculate the interface trap density, the admittance is first measured at a fixed gate bias in the depletion region from any of the two regions of the curve, i.e., above or below $f_{\mathrm {p}}$ . The value of the universal function $f_{\mathrm {D}}$ is then determined using the standard deviation of band-bending ( $\sigma _{\mathrm {s}}$ ) obtained from the curve [128, 129]. The interface state density is then calculated as [121]:

$(2.11) \begin{equation} D_{\mathrm {it}}\approx \left [f_{\mathrm {D}}(\sigma _{\mathrm {s}})q\right ]^{-1}\left (\frac {G_{\mathrm {it}}}{\omega }\right )_{\mathrm {max}}. \end{equation}$

Although the interface trap density can be directly deduced from measurements, the conductance method is not applicable to interfaces with a high interface state density such as in devices with high-k dielectrics. If the interface state capacitance $qD_{\mathrm {it}}$ becomes larger than the oxide capacitance, the measured impedance will be dominated by the oxide capacitance and $D_{\mathrm {it}}$ would be underestimated [130]. Another drawback of the conductance method arises during weak inversion, when the increase in conductance due to minority carrier generation-recombination may lead to overestimation of the interface trap density.