Predictive and Efficient Modeling of Hot Carrier Degradation with Drift-Diffusion Based Carrier Transport Models

Chapter 1 Introduction

One of the main concerns limiting the lifetime of semiconductor devices is hot-carrier degradation (HCD) [1, 2, 3, 4, 5, 6]. HCD is often assumed to be dominated by the interaction of carriers with the Si-H bonds which are formed at the Si-insulator interface during hydrogen annealing of the unpassivated Si bonds. The rupture of interfacial Si-H bonds leads to the creation of traps which then can capture charges and affect normal device operation. The charged traps perturb the electrostatics of the device, leading to a change in the threshold voltage ( $\triangle V_{\mathrm {th}}$ ). The interface defects can also act as additional scattering centers and lead to changes in the mobility ( $\mu$ ) and consequently to the degradation of linear and saturation drain currents ( $I_{\mathrm {d,lin}}$ / $I_{\mathrm {d,sat}}$ ), transconductance ( $g_{\mathrm {m}}$ ), etc. Although the first observation of this detrimental phenomenon dates back over four decades, the full physical picture is complicated and not yet completely understood, making predictive modeling of HCD difficult. As a result, quite often simplified empirical/phenomenological approaches are used [7, 8]. The successful among them are based on the so-called “energy driven paradigm” proposed by Rauch and La Rosa [9, 10, 11, 12]. These approaches introduce three main modes of HCD: (i) governed by the single-carrier (SC-process) mechanism of Si-H bond dissociation, (ii) driven by the multiple-carrier (MC-process) bond breakage process, and (iii) dominated by electron-electron scattering (EES). In the SC-process, a high energy carrier ruptures the Si-H bond in a single interaction. This process is assumed to be the dominant HCD mechanism in metal oxide semiconductor field effect transistors (MOSFET) stressed at high voltages (also referred to as classical HCD). The MC-process involves interaction of the Si-H bonds with multiple low energy carriers which is more typical for scaled devices subjected to HCD at lower voltages. However, it has recently been shown that the MC degradation mode can result in a significant contribution also in high-voltage devices with channel lengths up to $2\,\mu$ m [12, 13, 14], while the SC-process can be important even in decananometer MOSFETs [14, 13, 15].

Therefore, in order to properly represent the contributions of SC- and MC-processes one needs to be able to distinguish between hot and cold carriers. This information is contained in the carrier energy distribution function (DF) which can be obtained from the solution of the Boltzmann transport equation (BTE). There are two main strategies to obtain such a solution: the stochastic Monte-Carlo method [16, 17] and deterministic methods which are based on a representation of the carrier DF by a spherical harmonics expansion [18, 19, 20]. Both methods are numerically quite challenging even for ultra-scaled planar MOSFETs and especially in transistors with 3D architectures. Thereby, the computationally demanding simulations of the carrier energy distribution function are often avoided and the rates of the aforementioned processes are described by empirical formulas which are related to the macroscopic transistor characteristics [21, 22, 23, 12]. Note that these models are derived and calibrated using accelerated stress conditions. Therefore, it is possible that at real operating conditions the physical picture behind HCD is different, thereby making the models based on empirical expressions not predictive.

A remedy can be a physical HCD model which covers and links the whole hierarchy of the aspects related to HCD, namely (i) thorough carrier transport treatment which provides the information about the carrier energy distribution needed to (ii) model the microscopic mechanisms of trap generation and the corresponding rates, and to (iii) simulate the characteristics of the degraded devices [15, 24]. The most computationally expensive among these sub-tasks is the carrier transport treatment which requires a solution of the Boltzmann transport equation (BTE). This becomes even more challenging for large devices like laterally diffused metal oxide semiconductor (LDMOS) transistors. First of all, this is related to the typical dimensions of these devices, as compared to nanoscale complementary metal oxide semiconductor (CMOS) transistors, and thus to a mesh which contains a large number of cells. Second, complex transistor architectures with features like a bird’s beak, shallow trench isolation (STI) corners and non-planar interfaces, see Figure 1.1, as well as high doping gradients in different regions make the situation worse. Whereas in scaled devices the complexity increases due to increasingly important scattering mechanisms and complex 3D geometries such as those of finFETs. Furthermore, as we have shown [25, 26, 27], both single- and multiple-carrier mechanisms of bond dissociation provide substantial contributions to HCD in these devices.

In this context, simplified approaches to the solution of the Boltzmann transport equation such as the drift-diffusion (DD) and energy transport schemes appear to be very attractive [28, 29, 30, 31]. However, these approaches only provide some moments of the BTE rather than the full DF, which then has to be estimated using approximate analytical expressions. The most popular variant is the heated Maxwellian distribution and its modifications like a polynomial in the exponential [32], models developed by Cassi et al. [33], Hasnat and co-authors [34], Reggiani [35], etc. These carrier DFs are based on quantities such as the electric field or the carrier temperature obtained from a simplified moment-based BTE solution. Among them, the most successful model has been developed by Reggiani et al. which is suitable for the analytic description of DFs in LDMOS devices with a shallow trench isolation [35, 36]. The Reggiani model is able to represent the degradation of the device quite well when applied to HCD. Recently, the model has been demonstrated to work for LOCOS and STI-based LDMOS devices [37, 38]. However, the model has some difficulties in capturing the high-energy tail of the DF in the drain region and leads, therefore, to a less accurate description of the degradation in the drain area of the LDMOS. The inherent simplifications in all the above mentioned models limits their applicability and, thus, they cannot always substitute the solution obtained from the BTE. In this work, an analytical approach based on the physical mechanism is developed for DFs and HCD prediction.

The structure of the thesis is as follows: In order to precisely model the device degradation due to HCD, it is important to understand the difference between different reliability issues in semiconductor devices. Thus, the different degradation mechanisms and available carrier transport models in microelectronic devices are discussed in Chapter 1. The three main reliability issues discussed are: bias temperature instability (BTI), hot-carrier degradation (HCD) and time dependent dielectric breakdown (TDDB). BTI is mainly attributed to the creation of oxide defects and interface traps due to applied bias at elevated temperatures while the carriers are in equilibrium [39, 40, 41]. HCD, on the other hand, occurs due to the generation of defects at the oxide-semiconductor interface by the impinging high energy carriers [1, 7]. TDDB is a result of a percolation path in the dielectric which develops due to an applied field across the insulator [42, 43].

Chapter 2 is focused on HCD which is of most relevance for this work. This chapter also discusses the different experimental techniques used to extract interface state density profiles which are an important metric of degradation. Chapter 3 gives an overview of the existing HCD models, while Chapter 4 deals with the hot-carrier degradation model derived by our group [13, 25, 44]. Since the accurate description of HCD requires evaluating the carrier distribution function via a solution of the Boltzmann transport equation, special emphasis is given to the spherical harmonics expansion and the drift-diffusion methods. Thus, two versions of the HCD model have been used in this work, one based on carrier transport treatment by means of deterministic solution of the Boltzmann transport equation and another uses the simplified drift-diffusion scheme. In the latter implementation of our model an analytical expression is employed to approximate the carrier energy distribution function for the entire device. In Chapter 5, the results of both versions of the model are compared against experimental data for the n-and p-channel LDMOS transistors and a conclusion on the validity of the DD-based approach is drawn. The results suggest the efficiency of the DD-based method for predictive HCD simulations of LDMOS devices. The contribution of cold carriers to hot-carrier degradation is also analysed. The effect of cold carriers in our HCD model is twofold: firstly, a cold carrier term is used in the energy distribution function to account for low energy carriers, and secondly, the cold carriers determine the multiple-carrier process of Si-H bond dissociation.

Chapter 6 compares the different models for calculating the carrier DFs. The DFs obtained from the different approaches are used in our HCD simulations to predict the degradation in nLDMOS devices [45]. The simulated changes in device characteristics are compared to experimental data and conclusions on the validity of each model are drawn. Since all models use the same parameter set, the differences in the results can be directly traced back to inaccuracies in the approximation of the DF. Chapter 7 explores the limits of the DD-based method for obtaining the carrier energy DF. The analytical approach is used on planar devices with different dimensions and the HCD predicted by the SHE- and DD-based approaches are compared. The results suggest that the DD method to obtain the carrier DF looses its validity for devices scaled beyond 1.5 $\,\mu$ m. Chapter 8 deals with an extension of our DD-based model to decananometer MOSFETs by incorporating the effects of electron-electron scattering on the carrier distribution. In Chapter 9, some conclusions are drawn, while Chapter 10 discusses future refinements and an outlook towards predictive HCD modeling.

1.1 Bias Temperature Instability

Bias temperature instability refers to the time-dependent instability in transistors which accelerates when bias and temperature are increased. It is particularly observed when a high voltage is applied to the gate contact of a transistor at elevated temperature, while the other contacts remain grounded. Previously BTI was considerable only in p-channel MOSFETs, especially with SiON gate dielectrics, due to hole trapping and interface state generation,

but negligible electron trapping [1, 47, 48]. However, with the use of high-K dielectrics, both n- and p-channel MOSFETs can exhibit considerable BTI due to electron and hole trapping in the high-K and interfacial oxide layer [49, 50]. Another factor leading to pronounced BTI in modern devices is the aggressive down-scaling giving rise to high electric fields to maintain a reasonable subthreshold leakage. Increase in the density of integrated circuits for ultra large scale integrated systems on chips also leads to an increase in the power dissipation and self heating.

The BTI in n- and p-MOS transistors is observed when a positive or a negative voltage is applied at the gate and thus the phenomenon is referred to as positive bias temperature instability (PBTI) or negative bias temperature instability (NBTI), respectively. The consequence of BTI is a change in the threshold voltage in the inversion mode, thus, leading to a change in the drain current. BTI also affects other device parameters such as transconductance and gate-drain capacitance. In CMOS circuits this would mean performance degradation such as reduction of the switching speed. This degradation is usually attributed to chargeable defects, for instance the hydrogen bridge and the hydroxyl $E'$ centers [51, 52, 53]. The other contributors to BTI are interface traps. These defects are present directly at the interface (represented with a density $N_{\mathrm {it}}$ ) of the substrate and gate insulator in MOS devices [39, 40]. The capture and emission of charge carriers by these defects causes changes in the electrostatics of the device which disturb its functionality. For example, the threshold voltage in a p-MOSFET is given by [39]

$(1.1) \begin{equation} V_{\mathrm {t}}=\Phi _{\mathrm {MS}}-\frac {Q_{\mathrm {ox}}}{C_{\mathrm {ox}}}-\frac {Q_{\mathrm {it}}(2\Phi _{\mathrm {F}})}{C_{\mathrm {ox}}}-2\Phi _{\mathrm {F}}-\frac {Q_{\mathrm {S}}}{C_{\mathrm {ox}}},\label {eq:1} \end{equation}$

where $\Phi _{\mathrm {MS}}$ is the work function difference between the gate and the substrate, $\Phi _{\mathrm {F}}$ the Fermi potential, $Q_{\mathrm {ox}}$ ( $=qN_{\mathrm {ot}}$ ) the oxide charge density, $Q_{\mathrm {it}}$ ( $=qN_{\mathrm {it}}$ ) the interface charge density, $Q_{\mathrm {S}}$ the semiconductor charge density, and $C_{\mathrm {ox}}$ the oxide capacitance per unit area. The oxide and interface charges denote the charges trapped by corresponding defects and, thus, Equation 1.1 approximates the relation between the threshold voltage and the change in the oxide and interface charge densities. It should be noted that Equation 1.1 assumes that the oxide capacitance $C_{\mathrm {ox}}$ remains unchanged during stress [54]. A characteristic feature of BTI is recovery, meaning that upon the removal of stress the device parameters tend to attain their original values as shown in Figure 1.2. The difference between the original and recovered values of the parameters is often called the permanent component of BTI. In the past, the recovery of BTI was largely attributed to $N_{\mathrm {ot}}$ recovery on removal of stress, while the $N_{\mathrm {it}}$ were considered to remain unchanged during the recovery phase [55].

However, this differentiation is often debated and it was shown that $N_{\mathrm {ot}}$ also contributes to the permanent component of BTI [57], thereby making the characterization of BTI much more complex.

A majority of the modeling attempts focus on NBTI as it is a severe problem in $\mathrm {Si}\slash \mathrm {SiO_{2}}$ based devices. In this respect, the Reaction–Diffusion (RD) model and its extensions have been widely used [58, 59, 60, 61]. Within the framework of the RD model, the reaction phase consists of interface trap generation and release of hydrogen as a consequence. The reaction is diffusion-limited. The released hydrogen is then assumed to diffuse into the oxide during the stress. This diffusion is dependent on the stress time. During the stress phase the degradation, i.e. interface state generation, predicted by the RD model typically depends on stress time as $t^{n}$ [39]. However, the relaxation or recovery has not been adequately explained by any extension of the RD model.

The RD models have proven to be inaccurate and later studies have linked NBTI to reaction-limited processes like charge trapping and interface state generation [55, 62, 63, 64]. Some better descriptions were given by the double and triple well models where the diffusion of hydrogen is replaced by dispersive bond-breaking [59, 65, 66]. A more advanced model which was devised to explain the more complex experimental data was the two stage model [67]. This model suggested hole capture to occur in the gate oxide due to the presence of border traps instead of the Si/insulator interface. The introduction of time dependent defect spectroscopy (TDDS) has enabled detailed investigations of the charging and discharging of single defects. These investigations have led to the formulation of the four state model based on the non-radiative multiphonon (NMP) theory [68]. This model suggests the existence of two metastable states along with the conventional charged and neutral states. Within the NMP framework, the capture and emission time maps are derived using the carrier capture and emission time constants for the transitions between different states, shown in Figure 1.3. The distribution in the capture and emission time maps is mainly governed by the equilibrium occupancy difference which also describes the average contribution of a defect to the threshold voltage [69, 46]. The four state model not only explained the observations in BTI and TDDS experiments but also random telegraph noise (RTN) and flicker noise. These have been attributed to random exchange of charges between defects and the substrate during stationary conditions [70, 56]. The NMP model is highly effective in representing many more BTI characteristics when combined with a two well model for interface state generation.