5. Applications

FAST SWITCHING and high  $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ current ratio are the most important characteristics required for future nano-electronic applications. Based on the quantum transport model outlined in Chapter 4 both the static and dynamic response of CNT-FETs are investigated. Based on the result we propose methods to improve the functionality and performance of such devices.

In the first section the ambipolar conduction of CNT-FETs, which results in performance limitation, is studied in detail. We propose a double-gate structure to suppress this behavior. Simulation results indicate that a considerable improvement of device characteristics can be achieved by employing this structure. In this device type carrier injection at the source and drain contacts are controlled separately.

However, since the fabrication of single-gate devices is more feasible than their double-gate counterpart, we focus on such devices in the next section. Scaling of the gate-insulator thickness and the effect of relative permittivity of the gate-insulator on the performance of single-gate CNT-FETs have been studied in the literature [260,261,5].

We analyze scaling of the gate-source and gate-drain spacer length of single-gate CNT-FETs, which has not yet been studied in the literature. By increasing the gate-drain spacer length the ambipolar conduction decreases and the  $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio increases. Furthermore, the parasitic capacitances are reduced which results in reduced switching time. By increasing the gate-source spacer length both the on-current and parasitic capacitances decrease. We show that by optimizing this spacer length the performance of the device can be significantly enhanced. The results indicate that these effects can be very different from that in conventional MOSFETs.

Next we study a new device type, the gate controlled tunneling CNT-FET. The effect of the source and drain doping on the performance of these devices is investigated. We show that by using an asymmetric doping the  $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio increases.

Finally, the effect of electron-phonon interactions on the device characteristics is discussed in detail. In agreement with experimental data, our results indicate that electron phonon interactions can affect the DC current of CNT-FETs only weakly whereas the switching response of such devices can be affected significantly.

Subsections

• 5.1 Double-Gate Design
  • 5.1.1 Ambipolar Conduction
  • 5.1.2 Double-Gate CNT-FET
  
  
• 5.2 Asymmetric Single-Gate Design
  • 5.2.1 Gate-Source Spacer Length
  • 5.2.2 Gate-Drain Spacer Length
  
  
• 5.3 Device Optimization
  • 5.3.1 Gate-Delay Time of CNT-FETs
  • 5.3.2 Optimized Spacer Length
  
  
• 5.4 Tunneling CNT-FETs
  • 5.4.1 Symmetric and Asymmetric Doping
  
  
• 5.5 The Effect of Electron-Phonon Interaction
  • 5.5.1 Electron-Phonon Coupling Strength
  • 5.5.2 Phonon Energy
  • 5.5.3 Diffusive Limit
  • 5.5.4 Discussion

M. Pourfath: Numerical Study of Quantum Transport in Carbon Nanotube-Based Transistors