THE invention of the transistor in 1947 has started the exponential growth of an industry which is now, some decades later, a several hundred billion dollar industry. The first bipolar transistor was announced in December 1947 by William Shockley, John Bardeen, and Walter Brattain at Bell Labs. In 1956 the three researchers were honored with the Nobel Price in physics for their invention. The first metal-oxide-semiconductor (MOS) transistor and the first integrated circuits were demonstrated in the early 1960s. From that time on the development in the field of microelectronics was impressive. The integration density grew exponentially. This exponential growth was already identified in 1965 by Gordon Moore [1] as follows
``The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (...) Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer.``
Today, in 2007, we have more than 1 billion transistors on one single processor die. This high integration density has to be accompanied by stringent efforts to increase the reliability of each transistor, of the interconnect structure, the packaging, and the whole die to a maximum possible. The failure of a single transistor can lead to complete failure of the whole system.
Not only the integration density has been steadily growing, also the pressure on the industry to deliver short time-to-marked and therefore minimal research and development times for new technology nodes is increasing. This has led to intense efforts in the field of numerical simulation of the semiconductor manufacturing process and the resulting device structure, so called technology computer aided design (TCAD). It can reduce the number of test cycles with real semiconductor devices and drastically increase the possibilities to vary process parameters as doping concentrations, device geometries, materials and their composition to a minimum. Here, TCAD gives the opportunity to analyze the effect of process variation within hours instead of weeks for real processing.
The main target of this thesis is to extend the capabilities of the TCAD
framework by a very important degradation mechanism, the negative bias
temperature instability (NBTI). This degradation mechanism especially affects
p-channel MOS field effect transistors (MOSFETs) which are stressed with
negative gate voltages at elevated temperatures. NBTI has gained tremendous
scientific and industrial interest as it can lead to severe shifts of important
transistor parameters, as the threshold voltage or the drain current, and seems
to be accelerated in recent technologies which rely on nitrided oxides,
high-
dielectrics, and other novel approaches. The exact physical
background is still not completely understood but the general consensus is that
the
interface is damaged and interface traps and/or interface charges
and probably oxide charges cause the degradation.
The structure of this thesis is designed to guide the reader from the fundamental basics of semiconductor device simulation, over the most important degradation mechanisms leading to the thorough elaboration of the effect of NBTI. Presenting the state-of-the-art scientific understanding of this form of device degradation, a comprehensive model is proposed and evaluated by the simulation of a range of case studies.
Chapter 2 presents the fundamental equations for semiconductor device simulation and their derivation from Maxwell's equations and also analytic MOSFET approximations. Next, the most important generation and recombination mechanisms found in semiconductor devices are presented. Here, the main focus is laid upon the phonon transition, or Shockley-Read-Hall, mechanism. It is of special interest for modeling the carrier generation and recombination at silicon/dielectric interface traps which are caused by negative bias temperature instability. The third part of this chapter gives an insight into modeling of quantum confinement at the silicon/dielectric interface.
Chapter 3 focuses on the silicon/silicon-dioxide interface. It is of utmost importance for the proper operation of CMOS technology. NBTI affects exactly this interface and generates defects which are discussed in this chapter. Chapter 4 shows possible means of characterizing the interface using the charge pumping method, the DCIV method, and capacitance-voltage measurements.
Chapter 5 gives an overview of common degradation mechanisms affecting the dielectric layer in CMOS transistors. Sources of degradation outlined here are the damage caused by hot carriers, the dielectric wear-out and breakdown, and quantum mechanical tunneling. The problem of trap-assisted tunneling through highly degraded devices is described in detail. It causes not only additional gate leakage currents but also threshold voltage shifts due to trapped carriers in the oxide, comparable to NBTI.
The main part of this thesis is found in Chapter 6. Here the history of
negative bias temperature instability is presented along with the current
understanding of the physical mechanisms involved. Methods for measuring the
level of degradation are examined and common models trying to reflect the
physics of NBTI are presented and discussed. The last part of this chapter
presents the new model which was implemented in a numerical device simulator as
part of this work. This new model can achieve excellent agreement with
measurement data and is especially valuable for the evaluation of pure
dielectrics as used in power MOSFETs.
Chapter 7 gives case studies of the presented model which is compared to measurement data and achieves excellent agreement. The impact of NBTI on circuit performance is evaluated in transient and stationary numerical device simulations.