In this chapter a short summary of the history of the development of the metal-oxide-semiconductor (MOS) field-effect-transistor (MOSFET) will be given, followed by an overview of reliability issues in state-of-the-art MOSFETs. Finally, the focus of this work will be outlined and the structure of the thesis will be given.
Early concepts of amplifying devices employing the field effect were first proposed in the 1920s and 1930s by Lilienfeld [1] and Heil [2]. The effect was not well understood at the time and also manufacturing of such devices was not possible. It required further development of the understanding of semiconductor physics until the field effect could be demonstrated by Schockley and Pearson [3] in 1948. In the basic field effect experiments, as Schockley and Pearson performed, a few micrometer thin strip of semiconducting material was used, separated from a gate electrode by thin sheets of quartz, mylar, mica, barium-, or strontium-crystals. The semiconducting strip was contacted at its ends using metal electrodes. These Ohmic contacts allow a majority current to flow, with its amplitude determined by the density of the majority carriers in the semiconducting strip, which in turn can be controlled by a bias applied at the gate electrode. This enabled not only studies on the modulation of the majority carriers, but also on defects located at the surface of the semiconducting strip. However, employing the conduction of majority carriers significantly limits the geometry of such devices. The semiconductor strip has to be very thin, as otherwise the current flux is not confined to the region affected by the electric field but spread over a wider region. In this case the field effect is not observed anymore and the majority current can not be controlled by the gate bias. In case of silicon, the maximum strip thickness is around 3 µm [4].
An alternative application of the field effect aims at the creation of a so-called inversion layer, which consists of minority carriers. Such inversion layer devices do not suffer from this limitation, as the thickness of the inversion layer is limited by the penetration depth of the electric field. However, the Ohmic contacts used in the early devices did not enable the formation of an inversion layer, as minorities could only be provided by thermal generation in the semiconductor bulk. But the forming of an inversion layer has been observed as a parasitic effect in bipolar junction transistors (BJTs) that time, which enabled to explore this effect [5]. In 1955, Ross proposed electrostatic creation of an inversion layer in the base region of a BJT [6]. Another important observation made in the 1950s by Atalla et al., is the impact of the thermal oxidation on the interface trap density. By evaluating the high temperature oxidation of silicon surfaces it has been observed that the interface trap density can be significantly reduced [7]. The combination ob both, the exploration of the field effect and the initial attempts to create MOS structures paved the way for the successful development of MOSFETs in the 1960s.
The first MOSFET structures were shown by Kahng and Atalla in the 1960s [8, 9]. These early MOSFETs suffered from significant variations in their characteristics due to a high density of interface defects prevalent at the
Si/SiO
interface and also from of oxide charges originating from ionic contamination. The first commercial process enabling the fabrication of MOSFETs with stable characteristics was shown in 1963 by Deal [10]. One year later, in 1964, Miller and Barson found that the ion contamination can be considerably reduced using getters [11] and Kerr and Young observed that this could be improved further by applying an electrical field to the gate during annealing [12]. Further notable improvements in the 1960s were the introduction of complementary MOS (CMOS) technology by Wanlass [13], which enabled lower power dissipation in logic circuits compared to NMOS-logic, and eventually higher switching speed and density. Another
significant improvement of the fabrication processes has been achieved by the introduction of the polycrystalline gate [14], as now MOSFETs
could be produced self-aligned by using the gate as a diffusion mask for the source and drain doping processes. The introduction of the floating gate [15] paved the way for non-volatile data storage, and the DRAM cell invented by Dennard [16] enabled a high storage density for volatile memory. A further milestone for controlled device fabrication is the application of ion implantion [17] for creating doped areas, as this offers high flexibility in transistor design and improves the precision in controlling the amount and depth of the dopands
incorporated into the structure. A notable invention is also the charge coupled devices (CCDs) by Boyle and Smith [18], enabling a number of
applications, including shift registers and image sensing.
Since the 1970s, the continuous improvements of the fabrication processes and MOS technology has allowed decreasing the feature size of integrated MOSFETs from around 10 µm down to below 10 nm
today. This development required several updates of the techniques and equipment used for lithography as typical gate lengths became shorter than the wavelength of UV light. The enhancements include shorter wavelength light
sources, phase-shift masks, optical proximity correction and immersion lithography. Not only the geometry, but also the layer thicknesses had to be significantly reduced. For instance commercial insulating layers exhibit an oxide
thickness of only few nanometers. However, pure SiOor SiON insulating layers with a physical thickness below 2 nm exhibit a drastic increase in tunneling current. To mitigate this, high-k gate dielectrics have been introduced, which allow for smaller equivalent
oxide thicknesses without suffering the increased leakage currents. Another detrimental effect in scaled planar MOSFETS are short channel effects like drain-induced barrier lowering (DIBL) and gate-induced drain leakage
(GIDL). To suppress such short-channel effects, the principal shape of the MOSFETs has been altered, e.g. in FinFETs, to improve electrical control over the channel.
As device miniaturization seems to approach its physical limits, the focus towards further improvement of the performance in logic devices is shifting to novel materials and new concepts. Next to silicon, other materials have
recently emerged for applications in electronic power devices. For such applications, silicon carbide and gallium nitride show very promising properties. As both materials exhibit a larger bandgap than silicon, such devices can
sustain higher electric fields. An additional decisive advantage of SiC over Si is also the higher thermal conductivity, making SiC more suitable for high power applications. Finally, it is worth mentioning that 2D materials are also
considered for novel MOS devices. One advantage is that the interface between the 2D material and the insulator does not exhibit interface defects as these two materials are connected by van der Waals bonds, instead of having
covalent bonds as present at Si/SiOinterfaces. However, the development of such devices is still in its infancy and requires significant improvement of the fabrication processes in order to establish this technology.
At the time of writing, power MOSFETs based on SiC and GaN are commercially available, GaAs field-effect transistors (FETs) are available for high frequency applications and SiGe-on-insulator substrates are used in logic transistors to improve mobility and decrease leakage. Although the device performance is continuously improved, the presence of a number of defects cannot be avoided. As such defects can affect the long-term stable operation of devices, an understanding of their behavior and impact on the device performance provides an essential input for circuit and application engineers. Over the recent years, four main reliably issues have been distinguished and will be discussed next.
