The MOSFET is the fundamental building block for many of the technological advances of the last decades. Since its invention, the MOSFET has been continuously improved. The reliable operation of these devices under various operating conditions, e.g. biases and temperatures, is important for the stable operation of the circuits they are part of. Issues limiting the reliability and performance of modern MOSFETs include random telegraph noise (RTN), bias temperature instability (BTI), stress induced leakage current (SILC), and hot carrier (HC) degradation. Responsible for the observed degradation of the device performance in this regard are atomic scale defects which can be introduced during manufacturing or created during operation of the devices. These defects alter the function of the devices by capturing and emitting electric charges. The defects can be located in the insulating oxide of the transistor, at the interface between the oxide and the semiconductor, or in the semiconductor bulk. Most relevant for the performance of a MOSFET are the defects in the oxide and at the interface, which can exchange charges with either the conducting channel or the gate contact.
A number of models have been developed describing the charge trapping behavior of such defects, among them the Shockley–Read–Hall (SRH) model, the non-radiative multi-phonon (NMP) model and the recently proposed hydrogen release model. Detailed ab-initio studies of the atomistic nature of the defects can be performed using density functional theory (DFT) calculations and allow linking their properties to model parameters, while the influence of the defects on device performance can be simulated using TCAD tools employing the charge trapping models. To explain the statistical impact of the defects on devices, the defect centric model can be used. All of these methods, however, require characterization studies on sample MOSFETs to calibrate or verify them. Characterization of the defects is possible using a variety of methods, either probing whole defect distributions or single defects. Popular measurement schemes include methods investigating the defects’ influence on the channel current, e.g. RTN and extended MSM (eMSM), methods measuring the charging or discharging current of the defects, e.g. capacitance-voltage (CV) and charge pumping (CP) measurements, and physical characterization methods, e.g. the secondary ion mass spectroscopy (SIMS) and electron paramagnetic resonance (EPR) characterization. From the data obtained from applying these methods, defect parameters can then be extracted. Especially in the case of single defect measurements, the defect parameter extraction from the often noisy measurements can be quite demanding, and in particular for RTN measurements a number of different methods are available to do so. Single defect measurements are helpful in the development of physical defect models and allow to verify if they properly explain the defects’ behavior. Distributions of single defects can then be calculated to explain also the behavior of large area devices. To obtain the shape of these distributions one may either try to infer them from single measurements on large area devices containing the cumulative response of many defects or from a sufficient number of separate single defect measurements on small area devices.
In Chapter 6, two studies using different approaches of defect characterization to investigate statistical parameters of defects in two different commercial-grade silicon
technologies were shown. In the first study, RTN measurements were used together with an extraction methodology based on the Canny algorithm to find the distribution of the defects’ impact on the threshold voltage shift, the
trap level, and the vertical depth of the defects. This revealed a bimodal distribution of step heights in these devices, whose origin requires further work. In the second study on silicon devices, an array chip designed especially for
characterization purposes was used to conduct mixed BTI and RTN measurements. A methodology based on the defect centric model was then used to find the impact of various bias conditions on the degradation in these devices.
Aside from the studies on mature silicon technology, a study exploring single defects in novel devices manufactured using MoS
as a channel material was presented. For this study, RTN measurements were performed in a large temperature range and evaluated using an approach based on HMMs to obtain first insights into single defects in
experimental MoS devices.
Specialized test structures as the one studied in Section 6.2 significantly decrease the measurement effort required to study statistically significant numbers of single defects. Improved structures of this kind may allow the characterization of multiple devices in parallel and thus also reduce the time required for such studies. Further improvement of the methodologies used to extract the defects’ properties from the recorded data may enable such studies on devices with larger gate areas or higher defect densities.
CV measurements have been used for the characterization of interface defects, for oxide defects, however, faster methods of characterization are generally preferred. In particular when studying the creation or passivation of oxide defects, e.g. due to mechanisms involving hydrogen movement, measurement speed is not as critical a parameter. For this, CV measurements may prove useful as they provide the energetic distribution of the defects.
The charge trapping behavior of defects is currently mainly studied via their influence on the drain-source current. However, as outlined in Section 4.1.1, they also influence the gate current either by directly exchanging charge with the gate or by influencing tunneling currents. Studying these effects in conjunction with measurements of the channel current may provide additional insights into the defects’ behavior.
