Advanced Electrical Characterization of Charge Trapping in MOS Transistors

List of Figures

2.1 Illustration of P (math image) centers at the (100) Si/SiO $_{\mathrm {2}}$ interface. Shown are P ( $\ch{.Si+Si3}$ ) and P centers ( $\ch{.Si+Si2O}$ ). Yellow: Silicon, Red: Oxygen, Blue: Silicon dangling bond. The dangling bonds carry a net spin moment and are thus visible in ESR measurements. Recreated from [32]

2.2 Illustration of the channel carrier densities in a scaled device and the resulting current percolation path. (a) Random dopands lead to locally decreased carrier densities. The neutral defect has no influence on the channel. (b) The defect is now charged and increases the restriction of the percolation path, leading to a decreased drain current and a higher threshold voltage.

2.3 Ball-and-stick models of two candidates for hole trap in amorphous SiO $_{\mathrm {2}}$ . (a) The hydrogen bridge and (b) the hydroxyl E $^\prime$ center. Here, yellow are the silicon, red are the oxygen, and gray are the hydrogen atoms. Additionally, the blue clouds represent the spin density for neutral defects, i.e. the location of the unpaired electron, while for the positive defects it shows the distribution of the captured hole. Both defects may exist in four configurations, with two of them neutral (states 1 and 1 $^\prime$ ) and two of them charged (states 2 and 2 $^\prime$ ). To change between two states with the same charge, the defects transition between their regular and puckered configuration [43, 44]. For this, a silicon atom moves through the plane spanned by its three neighboring oxygen atoms. Transitions between the neutral and charged states additionally require a charge transfer with the substrate or gate. Originally published in [BSJ1] and adapted from [45]

3.1 Example of a Markov process with three states, together with the corresponding states $\vec {I}$ , the state vector $\vec {P}$ in equilibrium, and the transition matrix $\mathbf {K}$ .

3.2 Schematic band diagram showing the capture and emission processes for acceptor-like traps (Blue) and donor-like traps (Red). Electron traps change between neutral and negative charge states while hole traps change between neutral and positive charge. States of the defects are shown as they are prior to the indicated transition.

3.3 Kirton-Uren model illustrated in a configuration coordinate diagram. A defect exchanges an electron with the reservoir. The position of the parabola depends on the carrier energy. The capture barrier $\Delta E\sub {B}$ accounts for thermal activation of the capture process. Blue: Empty defect, electron in the conduction band. Red: Electron captured at the defect site. Dashed: Energy zero of the system: empty defect, electron at the Fermi level. Recreated after [51]

3.4 Parabolic potential energy surfaces (PESs) for the charged (red) and a neutral state (blue) as used in the NMP defect model, together with the parameters of the model.

3.5 Markov chain (a) and potential energy surfaces (b) of the four-state defect. In addition to the neutral and charged states 1 and 2, there is an additional metastable state for each charge state marked with a prime ( $^{\prime }$ ). Transitions between neutral and charged states are modeled using NMP theory, while transitions between states of the same charge are purely thermal transitions described using classical transition state theory. Changing the gate voltage shifts the trap level which leads to a shift in the PES relative to each other.

3.6 Illustration of the hydrogen release model. A number of precursor sites (orange) exist in the oxide, which become defects once they capture a hydrogen atom. Vice versa, in one of the neutral configurations of the defect (blue) there is a realistic probability for the hydrogen atom to detach from the defect (a). Once this happens, the hydrogen can diffuse in the oxide (b) and bond to another precursor (c). The high diffusion rate for hydrogen in SiO $_{\mathrm {2}}$ , together with a low barrier of hydrogen capture by the precursors leads to a low probability of free hydrogen at any time. Additional hydrogen is supplied by the gate at harsh stress conditions (d), leading to additional defects. States of the defects are shown as they are before the indicated transitions. Inset: Markov chain of the hydrogen release defect. Compared to the four-state defect there is an additional precursor state to or from which the defect can transition by emission or capture of hydrogen, respectively.

3.7 Experiment on long-term degradation of a $\SI {10}{um}\times \SI {10}{um}$ planar pMOS transitor. Measured permanent degradation component (circles), together with simulation results extracted using the hydrogen-release model (red). From [76]

3.8 Distributions of the defects per device and the step height per defect in the defect centric model. Left: The average number of defects in the devices is assumed to be Poisson distributed around a mean value $N$ . Right: The impact of the single defects on the threshold voltage shift is given by an exponential distribution with the expectation value $\eta$ . While the majority of defects ( $1-\frac {1}{e}\approx 63\%$ ) show step heights below $\eta$ , some defects produce much larger steps. The variance in both the number of defects and step height per defect underlines the fact that for small devices with few defects on average, some devices can show degradation much worse than the average device.

3.9 Left: Measured distribution of (math image) after stress in comparison with the defect centric model. Center: The one-sided BTI component gets smaller after stress due to decreasing $N$ . Right: The symmetric RTN component stays constant throughout recovery.

4.1 Schematic of a constant gate voltage measurement setup for channel conductivity based methods. The drain and gate voltages of the device are controlled by DACs. The gate voltage is applied directly to the gate of the DUT, while the drain current is supplied to the positive terminal of an OPAMP configured as an transimpedance amplifier. Its negative input terminal is connected to the drain connection of the DUT. The voltage output of the transimpedance amplifier, which corresponds to (math image) , is read by an ADC. Originally published in [BSJ1]

4.2 Schematic of a constant source current measurement setup for channel conductivity based methods. The drain bias of the DUT is controlled directly, while the gate bias is controlled by the OPAMP. The OPAMP circuit controls the gate bias of the MOSFET in a way that the source current equals the reference current defined by the DAC bias $-I\sub {s}R\sub {s}$ . Originally published in [BSJ1]

4.3 Top: Schematic of the measurement system [39] employed for this work. Analog and digital subsystems colored in blue and orange, respectively; control signals omitted for clarity. The system consists of a 19" rack case with 12 slots which can be equipped with a number of different inserts. The inserts connect to a back-panel which provides analog and digital power, a number of signaling lines, an I $^2$ C bus and individual USB lines. For the methods based on channel conductivity as outlined in this section, the constant gate voltage scheme (Figure 4.1) has been used. Bottom: Using the system, the channel current can be measured either on the source terminal or on the drain terminal of the device as shown in the lower part of the figure. Additional inserts can be equipped to measure e.g. the gate current.

4.4 RTN measurements in the time domain (left) and frequency domain (right). In large devices (top), the noise signal in the time domain corresponds to a 1/f spectrum in the frequency domain. In small devices (bottom), due to the small number of defects and the large influence of each defect on the channel current, individual steps can be observed. In the frequency domain, the Lorentzian PSDs of the individual defects which make up the 1/f shape in large devices might still be distinguished. Originally published in [BSJ1]

4.5 Energetical window for RTN characterization shown in a Si-SiO $_{\mathrm {2}}$ band diagram. Defects located close to the Fermi level randomly exchange charge with the channel and produce RTN. Defects located far above (below) the Fermi level will be neutral (charged) for most of the time. The brief phases where they are charged (neutral) will most likely be too short to sample. Originally published in [BSJ1]

4.6 Flow chart illustrating parameter extraction from single defect RTN measurements. To obtain parameters suitable for defect simulation, the RTN signal parameters for each defect first have to be extracted from the measurements. Using these parameters, physical defect parameters such as their trap levels can be obtained using analytical estimates or TCAD simulation.

4.7 Gate and drain biases during a MSM measurement. After an initial measurement, phases of stress and subsequent measurements are performed. This allows to characterize the degradation due to the applied stress conditions. In this example, degradation due to gate bias stress is characterized using (math image) () measurements.

4.8 Illustration of (math image) () characteristics of a device before and after BTI stress. From this, the threshold voltage shift , changes in the sub-threshold slope, the off-current and the transconductance can be obtained. Originally published in [BSJ1]

4.9 Gate bias and drain current during an eMSM measurement. Phases of stress alternate with phases of relaxation. During relaxation the drain current or threshold voltage shift is recorded. This allows to observe the impact of stress on the device behavior and also to understand the following relaxation behavior.

4.10 Measurement data (circles) and simulation data (lines) for a BTI eMSM experiment. Note that the simulations suggest that a significant part of the threshold voltage shift due to stress already recovered before the first recovery measurement point is taken, underlining the need for fast measurements.

4.11 Hot carrier stress. Unlike BTI stress, a non-negligible source-drain bias is applied, causing carriers to accelerate towards the drain. This causes damage at the interface or secondary carrier generation.

4.12 Measurement windows for RTN and TDDS single defect characterization, shown for an exemplary defect. While RTN allows to characterize a defect at gate voltages close to $\Ef = \Et []$ , TDDS allows to measure its charge capture time at biases above this point and its charge emission time at biases below that point. By characterizing the defect using both methods, a comprehensive picture of the defects’ behavior can be obtained. Originally published in [BSJ1]

4.13 Gate and drain biases during an on-the-fly measurement. A small drain bias is applied for the duration of the measurement. At the same time, the gate bias is pulsed to measure selected points on the (math image) () curve. This keeps the interruption to stress at a minimum and thus allows to observe the degradation of the MOSFET.

4.14 Hysteresis measurements on a 4H-SiC nMOSFET with varied starting voltage (math image) and constant high voltage . Decreasing increases the hysteresis width. Data originally published in [99]

4.15 Schematics of a circuit as might be used for the charge based methods. With this setup, all signal processing has to be done in software. Particularly for CV measurements, part of the impedance extraction might be performed in hardware. In CP measurements, a hardware integrator might be used.

4.16 Top: Schematic of the measurement system [39] employed in this work, equipped for the measurement methods presented in this section. Analog and digital subsystems colored in blue and orange, respectively; control signals omitted for clarity. As compared to Figure 4.3 for channel current measurements, an additional sampling unit included to measure the phase of the input signal for CV and DLTS measurements. Bottom: Possible configurations for gate and bulk current measurements. For CV measurements both the gate or the bulk current can be used to measure the MOS capacitance. Especially when testing devices on a wafer this decision may however influence the noise level of the measurement. Source and drain terminals—if available on the test structure—may either be shorted to bulk or supplied separately (as shown), in case the gate current is measured optionally with or without the AC signal. Depending on the chosen configuration the gate-source and gate-drain capacitances may be included in the measurement.

4.17 Capacitance-voltage measurement. (a) DUT connected for measurement. (b) DUT in the various operation schemes with illustrated equivalent capacitance. In the depletion regime there are no free charges close to the interface. This can be interpreted as an increase in spacing between the plates of the equivalent capacitor. This in turn lowers the capacitance and gives the CV curve its characteristic shape. (c) Voltage and current signals during measurement. The phase and amplitudes of the voltage and current signals give the sought-after impedance. The offset voltage is swept in a staircase-like manner during the measurement. (d) Exemplary results of a CV measurement at multiple frequencies. The accumulation and inversion branches almost reach the oxide capacitance, while the capacitance in depletion is much lower. The inversion branch is generally steeper than the accumulation branch.

4.18 Extraction of the phase difference from a CV measurement. The current signal is mixed with the original voltage signal (left) and a phase-shifted signal (right). This gives signals with their sum and difference frequencies, i.e. $2\omega \sub {0}$ and $0\omega \sub {0}$ . After low-pass filtering or integrating, the DC I and Q signals which are proportional to the imaginary and real parts of the current remain.

4.19 The CP technique. (a) DUT during measurement. During the high bias phase defects charge with minorities supplied from source and drain. In the following low bias phase, the minorities are emitted and recombine with majorities sourced from the bulk. Their amount is measured as the bulk current. (b) Gate voltage and bulk current during measurement. (c) Gate voltage parameters for the two measurement schemes. (d) Illustration of a measurement result.

4.20 Illustration of deep-level transient spectroscopy using rate windows. As the temperature of the sample is increased, the time constants of defects in the device decrease. Once the response time of a defect band coincides with the chosen rate window given by $t\sub {1,2}$ , the difference between the capacitance at these points—the DLTS signal—increases. At even higher temperatures the defects responses get too fast and the signal decreases again.

4.21 DCIV measurement in the top emitter configuration. The drain and source diodes are slightly forward biased, causing minority injection into the space charge region. As the voltage is swept from accumulation to inversion, defect charges recombine with the injected minorities. This causes majorities to move towards the space charge region, in turn creating a measurable bulk current. The scale of this current depends on the number of defects discharging, as illustrated on the right.

4.22 Principle of EPR spectroscopy. (a) A sample is placed in a homogeneous magnetic field and irradiated by microwave radiation. (b) The magnetic field causes the energy levels of unpaired electrons to split due to the Zeeman effect. When the split caused by the magnetic field coincides with the microwave energy, the absorption peaks.

4.23 Principle of XPS. (a) X-ray photons are directed at the target. Upon collision they remove an electron from an atom. The electron moves to the sample surface and is emitted with an kinetic energy $E\sub {k}$ . The binding energy of the electron can then be calculated from the detected energy and the work functions of the sample and the detector. The probed depth can be influenced by the angle of the detector. (b) The resulting peaks in the observed binding energies can be linked to the targeted species and their concentrations. Graph from [112]

4.24 Principle of SIMS. (a) The sample is sputtered with ions. Upon collision they remove ions from the sample. These secondary ions are then analyzed in a mass spectrometer. (b) Exemplary results: the composition of the removed material over time is seen in the output of the mass spectrometer. Measurement results from [113]

5.1 Exemplary RTN signals (a) extracted using histograms (b,c) and time lag plots (d,e). The original RTN signal is shown in blue. The corresponding histogram (b) shows four partially overlapping peaks, indicating two defects. The time lag plot (d) shows the same peaks, but with better separation. In addition, the transitions between the states are shown in the off-diagonals. For the orange signal, a linear drift of 1.5 µV/s was added to show the influence of drift and low-frequency noise. Due to the drift, both the corresponding histogram (c) and time lag plot (e) show deformed peaks and it becomes difficult to distinguish the small defect. Originally published in [BSJ1]

5.2 The BCSUM algorithm applied to an exemplary signal $r$ . The columns show the initial step (left), and the first recursion for the first part (center) and second part (right) of the signal. Top: Signal used during recursion. Middle: CSUM signal of the original data. Bottom: Histogram of $\gamma ^*$ values obtained from the bootstrapped data, together with the $\epsilon = 0.9$ quantile value (Black), and $\gamma$ from the original data (Red). Recursion ends when $\gamma < \gamma ^*_{\epsilon }$ , as is the case in the bottom center plot.

5.3 The Canny algorithm for edge detection demonstrated for an exemplary measurement trace. The input signal $f(t)$ is convoluted with the first derivative of a Gaussian pulse with a chosen variance $G^{\prime }$ . This gives a signal $H(t)$ , which exhibits peaks corresponding to the steps in the original signal. All peaks above a chosen threshold are recognized and used to mark the positions of the steps in $f(t)$ . The height of the peaks can be obtained from the original signal or from the height of the peaks. Modified from [BSJ1]

5.4 Comparison of the Canny edge detector and the BCSUM method for signals with different noise floors. The signal contains two defects with step heights of $\eta _1\approx \SI {0.25}{mV}$ and $\eta _2\approx \SI {0.55}{mV}$ . (top) Original signal, both methods agree within 2% of absolute deviation of the extracted charge transition times. (middle) $\sigma =\SI {0.1}{mV}$ of added noise. The extracted capture time increases as the algorithms miss shorter transitions. (bottom) $\sigma =\SI {0.2}{mV}$ of added noise. With a noise level similar to the step height of the extracted defect, spurious transitions affect the detections while proper steps are missed, leading to false results.

5.5 The measured drain current can be described by the evolution of the underlying Markov chain(s) of the defects. The reverse, however, may not be true. If reconstruction of the individual defect states is not possible from the recorded drain current data, a hidden Markov model in conjunction with the Baum-Welch algorithm may be used to estimate the model parameters, i.e. transistion probabilities $\mathbf {P}$ and emissions $\vec {\mu }$ .

5.6 Defects found from TDDS measurements. Recovery traces (top) are analyzed using a step detection algorithm and the steps are plotted in the step height–emission time plane (bottom). If enough traces are plotted, clusters will form for each defect which emitted during recovery. The clusters are distributed exponentially in time and normally in step height. To obtain the capture time of the defects, measurements at varying stress times have to be performed. From [135]

5.7 Illustration of charge capture time extraction from a TDDS measurement. Assuming a low occupancy of the defect at recovery conditions and a sufficient relaxation time, the average occupation of the defect at the end of the stress phase equals the probability of observing the defect discharging during recovery. By plotting this occupancy, i.e. the ratio of the number of emission events over the number of measurement repetitions, over the stress time, the exponential CDF for charge capture can be obtained. The charge capture time of the defect at the stress condition can then be extracted by fitting the theoretical distribution.

5.8 Schematic CV curves of a pMOS transistor, affected by defects located close to the conduction band. (a) Defect free CV curve. (b) Fixed charges or defects with $\tau f\sub {sweep} > 1$ shift the CV curve along the voltage axis. (c) Defects fast enough to react to the DC sweep but too slow to react to the AC frequency cause a stretch-out of the CV curve. (d) Defects fast enough to react to the AC frequency cause additional capacitance in the CV curve. In general, a superposition of these effects will be obtained, depending on the chosen measurement parameters.

5.9 Equivalent circuits for CV measurements in the different regimes. (a) General equivalent circuit. (b) Schematic CV-measurments for varying measurement conditions. (1–4) Accumulation, depletion, low-frequency inversion and high-frequency inversion equivalent circuits. To obtain the low- and high-frequency curves (blue and orange), the DC sweep rate has to be slow enough for the minority carriers to follow, otherwise the deep depletion curve (red) is obtained. If in addition the AC frequency is low enough for the minority carriers to respond, the low-frequency curve is obtained.

5.10 MOSCAP in depletion between low and high frequency regimes for a single interface defect. (a) Equivalent circuit with lossy interface defect represented by a series RC circuit. (b) Simplified circuit with equivalent parallel capacitance and conductance. (c) Behavior of C (math image) and G with varying measurement frequency. At low frequencies, $C\sub {P} = C\sub {b} || C\sub {it}$ and at high frequencies $C\sub {P} = C\sub {b}$ , in both cases $G\sub {P}/\omega \approx 0$ . At the corner frequency $\omega \tau =1$ , however, $G\sub {P}/\omega$ peaks at $C\sub {it}$ . This behavior is exploited in the conductance method [4].

6.1 Illustration of large area (a) and small area (b) devices with oxide defects randomly distributed in the SiO $_{\mathrm {2}}$ layer. Devices with a smaller gate area have on average a lower number of defects, but the average impact of the defects is larger. This leads to a similar mean degradation for both types of devices, but a much larger variance among the small devices. Originally published in [BSJ2]

6.2 Transfer characteristics of the $\approx$ 300 devices measured. Shown are the individual transfer characteristics in gray and the average in blue. The bias and current range in which RTN has been measured is highlighted. Originally published in [BSJ2]

6.3 An example of a short RTN trace. Even though this is the faster kind of the measurements performed, the noise level at around 0.15 mV is low enough to clearly see the trapping of two defects in the signal. Originally published in [BSJ2]

6.4 Example of the Canny edge detector used on one of the long (1 ks) RTN traces. The original (math image) signal has been convoluted with the first derivative of a Gaussian pulse to yield a signal $h$ which has peaks at the positions of the steps. Local maxima above a selected threshold give the positions of the steps, their magnitude $\eta$ has been taken from the original signal. Originally published in [BSJ2]

6.5 Complimentary cumulative density function of the step heights observed in the measurements. The distribution seems to be composed of two separate exponential distributions with mean values of 0.39 mV and 1.09 mV. Originally published in [BSJ2]

6.6 Examples of the capture and emission time dependence on gate bias and temperature, for two defects which have been characterized in more detail. Originally published in [BSJ2]

6.7 Distribution of the extracted vertical positions, measured from the interface, and trap levels for around 100 defects. The extracted energy peaks at around 0.4 eV above the Fermi level, which is close to the conduction band edge during the measurements. The distribution of the depths of the defects in the oxide shows a maximum at 0.6 $t\sub {ox}$ , which is where the effective trap levels of the defects coincide with the Fermi level. Originally published in [BSJ2]

6.8 Simulated band diagram showing the defects extracted using the estimations for depth and trap level. In addition, defect bands for SiO $_{\mathrm {2}}$ from [49] are shown in gray. Originally published in [BSJ2]

6.9 Distribution of the vertical positions, measured from the interface, and trap levels, referenced to the Si midgap, extracted using both the estimation approach and TCAD simulations. The simulation results show a narrower distribution in position and indicate that the defects are slightly closer to the interface compared to the estimations. The extracted trap levels are slightly lower as well, peaking ≈0.3 eV above the conduction band edge. The distribution of trap levels which have been measured covers mainly the lower half of the distribution obtained in [49]. Originally published in [BSJ2]

6.10 Layout of the signal lines of the array which have been used for defect characterization. The gate terminals of the transistors in each row can be switched between externally supplied on- or off-biases using on-chip logic. Likewise, the drain terminals can be switched for each transistor column. This allows to address and thus to characterize each individual device in the array. The bulk and source terminals are common for all devices. More details about the array structures can be found in [141]. Originally published in [BSJ3]

6.11 A set of (math image) () curves recorded on the long devices (shown in blue). In addition, the mean and variance are given in white and red. From the curves for each device, the gate bias during relaxation has been determined based on a chosen relaxation current $\ensuremath {{I}_{\mathrm {D}}}{}\sub {,r}=\SI {100}{nA}$ . Originally published in [BSJ3]

6.12 A set of (math image) () mapped from () using the corresponding set of () curves (shown in blue). The mean and variance are given in white and red, respectively. The vertical lines indicate moments in time when the distributions of have been drawn for further analysis. Originally published in [BSJ3]

6.13 Degradation in (math image) recorded 1 ms after 10 s of stress at $\ensuremath {{V}_{\mathrm {G,str}}}=\SI {-1.45}{V}$ . Top: for each device as positioned in the matrix of short devices. Bottom: averaged over a number of devices. The plots show neither defective rows nor columns, nor clusters or overall inhomogeneities of the extracted degradation of the threshold voltage. Originally published in [BSJ3]

6.14 CDFs of (math image) during recovery. Blue: measured, Red: calculated. Most devices exhibit positive degradation ( $-{\ensuremath {\Delta V_{\mathrm {th}}}}> 0$ for pMOS) after stress due to BTI, while for some devices RTN causes the reverse $-{\ensuremath {\Delta V_{\mathrm {th}}}}< 0$ . Originally published in [BSJ3]

6.15 Extracted parameters obtained from the short devices after $\ensuremath {t_{\mathrm {r}}}=\SI {100}{ms}$ of recovery. The average step height $\eta$ ( $\times$ ), as well as the average number of RTN charges $N\sub {RTN}$ ( $\diamond$ ) remains constant over all sets. The average number of charges captured due to BTI $N$ ( $\bullet$ ) depends on stress bias and stress time as expected. Originally published in [BSJ3]

6.16 Average number of captured defects $N$ (shade) extracted 2 ms after stress release, over stress time and gate bias. The crosses indicate the measurement points, the dashed lines are contour lines separating the iso-surfaces. For weak stress conditions, only a fraction of the devices exhibits a charged defect after stress. Originally published in [BSJ3]

6.17 Average number of captured defects $N$ (shade) extracted after stress at $\vg =\SI {-1.45}{V}$ , over stress and relaxation time. The lines are contour lines separating iso-surfaces for the number of charged defects. Only for short stress times, full recovery can be observed in a relatively short relaxation time window. Originally published in [BSJ3]

6.18 Average degradation of the short devices during sets of stress at various gate biases. The simulation data shown as lines and the measurement data given by the points agree well, except for the first moments after short stress which show unusual negative (math image) shifts in the measurement. The origin of this behavior remains open at this point and requires further experimental and simulation efforts. However, the simulations qualitatively explain the trend of the measurements. Originally published in [BSJ3]

6.19 Average number of captured defects $N$ (shade) simulated after stress at $\vg =\SI {-1.45}{V}$ , over stress and relaxation time. The lines are contour lines separating iso-surfaces for the number of charged defects. The dashed line indicates a ten-year time frame. Originally published in [BSJ3]

6.20 Dependence of the average number of charged defects $t\sub {r} = \SI {100}{ms}$ on the stress gate-bulk voltage (math image) for measurements with pure gate stress and measurements with part of the stress voltage applied to the bulk ( $\vg = \SI {-1.3}{V}$ ). Both stress cases have a similar effect on the degradation. Originally published in [BSJ3]

6.21 Evolution of the average number of charged defects during recovery after $\ensuremath {t_{\mathrm {s}}}= \SI {100}{ms}$ stress at a number of gate-bulk voltages. Points show the measurements after pure gate stress while crosses show measurements with $\vg = \SI {-1.3}{V}$ and varied (math image) . Again, both stress cases seem to have a similar effect. Originally published in [BSJ3]

6.22 Dependence of the average number of charged defects on the drain bias. Left: After stress and $\ensuremath {t_{\mathrm {r}}}= \SI {100}{ms}$ of recovery. Right: During recovery after $\ensuremath {t_{\mathrm {s}}}= \SI {100}{ms}$ of stress. The mild drain bias stress applied does not seem to significantly affect the device threshold voltage degradation. Originally published in [BSJ3]

6.23 Colorized scanning electron microscope picture of one of the studied devices. The source and drain contacts are shown in yellow, below them is the structured MoS (math image) layer, shown in green. Originally published in [BSJ6](supporting material)

6.24 (a) Schematics of the devices used during measurement. Few layers of MoS (math image) are located on top of a SiO wafer. Source and drain have been contacted on top, while the channel has been controlled using the back gate. (b) Transfer characteristics () of an exemplary device with the subthreshold slope of $S\approx \SI {1.1}{V\per dec}$ . (c) Output characteristics (math image) () for the same device. These devices show normally-on characteristics. Originally published in [BSJ6]

6.25 Impact of single defects on different device characteristics: (a) Steps in the drain current of a transistor during (math image) () sweeps, equivalent to around 300 mV in . In large area devices many such defects would be visible as hysteresis, leading to a similar width of the hysteresis, but the individual contributions would not be observable. (b) A defect causing RTN. The stochastic behavior of the defect causes a large variety of charge capture and emission times. (c) Similar to (b), but this defect shows a significant gate bias dependence. (d) A defect showing aRTN, periods of noise are separated by periods of inactivity. The Markov chains necessary to model the respective defect’s behavior are shown in the insets (b) and (d). aRTN can not be described using a two state model and, in this case, needs an additional neutral state. Originally published in [BSJ6]

6.26 Capture and emission times extracted for four defects (symbols) and fits (lines). The charge transition times of defects A and D show a significant dependence on the gate bias, while the charge transition times of defects B and C seem to be unaffected by the gate bias. Defect B, which shows aRTN, is described using two sets of transition times due to its additional meta-stable state. The fits for defects B to D are from numerical simulation, while the fit for defect A is a linear fit. This is due to the current inability to simulate these devices at the low temperature at which defect A was measured. Originally published in [BSJ6]

6.27 The SRH and NMP defect models both widely used for the description of interface and oxide defects. (a) The mechanisms for charge transfer as outlined in Section 3.1. (b) Simulations of the capture and emission times of defects placed at a distance of 2 nm above and below the channel. It can be seen that due to the lack of a backward energy barrier the SRH model, only one of the charge transition times features a meaningful temperature and bias dependence at any voltage. The SRH model can not describe the strongly voltage dependent capture and emission times as observed for defects A and D. For defect C the temperature dependence of both capture and emission time can not be described by the simple SRH model. Finally, multi state defects such as defect B can not be described at all using the simple SRH model, as it is limited to a defect with only a charged and a neutral state. Originally published in [BSJ6]

6.28 Extracted spatial and energetic positions for defects A-D shown in a band diagram simulated for a device considering a 6 nm thin MoS (math image) layer. Defects A and D are located below the channel, while defects B and C are on top of it. The gate bias used for simulation was 1.2 V (opaque) and −4.2 V (semi-opaque). The charge transition times for defects A and D change with the gate voltage as their position relative to the Fermi level shifts. The gray lines depict defect bands extracted for SiO (math image) [BSC6]. Originally published in [BSJ6]