Abstract

-Integration is a novel technology in microelectronics and a necessity for the development of systems with enhanced performance with respect to size, speed, and power consumption. Thereby, the individual chips are stacked on top of each other, thus shortened electrical connections (interconnects) are possible. For the connections between the stacked chips novel electrical connection elements such as open through-silicon-vias are utilized. As all interconnect structures also these suffer from electromigration. Electromigration is the directed material transport in metals triggered by the nowadays common high current densities. At locations where material transport occurs, this leads to significant mechanical stress. The material transport can also lead to an interruption in the circuit. Electromigration mediated line failure with respect to line disruptions can arise from two different modes. In the first mode the mechanical load leads to a crack across the interconnect and through this to an interruption of the conducting connection, which results in an abrupt resistance jump. In contrast to this, in the second mode, the mechanical stress leads to the formation of a void, thus to a hollow region where metal can no longer be found which does not fully interrupt the metal track and thereby does not generate a line failure. This void can further migrate and grow in the metal, which with time increases the line resistance, until the specification of the integrated circuit is exceeded.

Traditionally interconnect structures are tested experimentally under accelerated test conditions. These experiments last very long and the planing must be very carefully carried out, in order to ensure meaningful results for the evaluation of the reliability. Therefore, the increased utilization of models and simulation of this phenomenon is an important tool to develop integrated circuits more economically regarding time and cost.

In this work an electromigration model was implemented in a commercial software in order to ensure the easiest and broadest exploitation in industry. This software is based on the finite-element-method. For this the newest models were considered, which allow for the simulation of both above-mentioned interconnect failure modes. For the implementation of void evolution a phase-field-model was facilitated. This allows for the simulation of voids without requiring remeshing after the void surface movement. This is possible, since the void and the interconnect metal lie within the same domain and the distinction is realized only through the value of the order parameter.

Furthermore, for the first time, this implementation for the assessment of the durability of an open through-silicon-via under electromigration was employed. In the first step the regions were localized which experience the highest electromigration load. They are found at the locations were the current density is highest and subsequently current crowding appears. These locations are found especially in corners and edges of the conducting structure, which are particularly pronounced at the overlapping area of the aluminium and the tungsten, which realizes the galvanic connection. Further is the vacancy flow through electromigration from the the aluminium to the tungsten blocked, since tungsten possesses a much higher durability against electromigration. Thus, vacancies gather close by the interface and a mechanical stress is formed. Subsequent thereto more vacancies are accumulated in the entire aluminium region and the mechanical stress rises further. For the occurrence of a crack formation a threshold was defined and simulations for different current values were performed. The gained times to failure were used to calibrated a compact model via the Black equation and showed good agreement in comparison to Black’s predictions. Also the occurrence of a void and its time evolution have been simulated. For this purpose previous simulations were continued and a void was placed at the location were the highest mechanical stress was observed. This simulation revealed that the void started to migrate towards the aluminium/tungsten interface and after reaching it further grew in size. Thus, the resistance increased, until the metal line showed a disruption which lead also to an abrupt resistance jump. Also these simulations were carried out for different current values and fitted with the Black equation. These two fitted compact models allow the prediction of the time to failure for the structure under consideration with different parameters (e.g. current density, temperature) and therefore are an important tool for the development of integrated circuits.