6 Summary and Outlook

For many decades Moore’s law has been the main driving force behind transistor scaling and miniaturization efforts in the semiconductor industry. For each technology node the technological problems become more pronounced and will inevitable reach fundamental physical limits in the near future. Thus, alternative trends in technological advancements, which attempt to deal with the integration of devices beyond memory and logic, dubbed More-than-Moore, gain in importance. One of those trends is the addition of technologies which do not scale according to Moore’s Law but nevertheless add functionality and complement to the trend to integrate digital logic, analog/RF, memory, sensors, actuators, bio chips, etc. in a single package. This requires the threedimensional stacking of different technologies by using TSVs. The resulting benefits are denser device packaging, lower power consumption, and reduced RC-delay.

Although TSVs present many advantages, there are still significant reliability concerns with this technology, such as permissible thermal budget, mechanical stability, process variability, and device reliability, which must be addressed before mass production is viable. One of the main concerns for the reliability of open TSVs is their degradation under EM.

This work concerns itself with the quantum mechanical understanding of EM. Furthermore, the development of the continuum mechanical descriptions of EM including the material flow and the thereby arising long-time failure issues is addressed. Finally the state of the art models, which cover the two different modes of failure are presented and their implementation in a commercial tool is described. The two failure modes differ in the way the device malfunction is triggered, as previously studied in dual-damascene interconnects. In the first mode a crack interrupts the conduction of the metallization structure due to an increased mechanical stress, while in the second mode a void is formed which does not immediately trigger a failure. This void migrates and grows inside the metallization, until its induced resistance overcomes a critical value needed for the system to operate uninterruptedly. In this study it was found that open TSV structures are prone to the same modes of failure as interconnects, while particular attention must be paid to the metal-metal interfaces.

In order to assess the reliability of a state-of-the-art open TSV structure, the EM through the metal layers in the TSV is analyzed. Two different metals are employed in the TSV design: aluminium for the top and bottom wafer contacts and tungsten for the current conduction through the wafer. The first step was the analysis and identification of the parameters showing the highest EM impact and their relations to the adjoining metal layers. In order to achieve this the interface behavior between the metals was studied to determine the worst case scenario. It was found that, for certain material combinations, a blocking behavior between the metals leads to a vacancy pile up at the interface resulting in an increased stress, which eventually triggers one of the two possible failure modes. This worst case is unfortunately the scenario when using a metal combination of tungsten and aluminium as employed in the considered open TSV structure. Therefore, it was found that a vacancy pile-up and thereby increased stress can be found at the top and bottom of the TSV, where the tungsten and aluminum layers are in contact.

Since EM is driven by the divergence of the current density, locations where current crowding occurs are highly relevant. Therefore, these locations were identified and are typically situated at corners and sharp edges. They are further augmented at interfaces with conductivity discontinuities. As this is a feature found in the particular device under investigation a variation of the geometry and conductivity was carried out in order to investigate methods to minimize the current crowding. For the studied device, current crowding was found to be most pronounced at the tungsten/aluminium overlap at the TSV top. As a general rule regarding overlapping metal lines the layer with the higher resistance should have a proportionally higher layer thickness to achieve a more homogeneous current density at the interface. This was found not to be the case for the studied structure, meaning that increasing the tungsten thickness would alleviate the interface current crowding.

Due to the high aspect ratios present in the TSV, a fully three-dimensional EM simulation of the entire structure using the finite element approach is only manageable with a fairly coarse mesh, reducing the accuracy of the results. Therefore, only a segment of the TSV structure was selected for detailed analysis, taking into account the current crowding simulations carried out previously. In addition, considering the fact that tungsten has a higher EM resistance than aluminium, a separate consideration was made for the top of the TSV. These simulations revealed the locations, where the highest tensile stress is located. The location is typically close to the interfaces between the aluminium and the tungsten as well as the aluminium and the silicon dioxide. Void nucleation or cracking will appear there as soon as a critical threshold stress is exceeded.

Assuming a critical stress in the order of the time to failure varies between about 110 days and 65 days under accelerated conditions, while the applied current is varied from to , respectively. The results were further used to calibrate the well known Black equation. This calibration showed the validity of the compact model based on Black equation and allows for an extrapolation to normal operating conditions for the technology under consideration and thus completes the assessment of the first mode of failure under EM.

Following this simulation the void evolution model was employed to examine the second failure mode under EM. Since the phase field model allows for the simulation of the void propagation without computationally expensive remeshing, it was implemented in the finite element code for the second failure mode to study open TSV structures. For the study an initial void was placed at the locations where the previous simulations showed high stress levels. This void begins to migrate in the aluminium in the direction of the current, while continuously increasing the resistance of the metal line.

While in the initial failure mode a critical stress determined failure, the mode studied in the second section deals with a failure due to an increased resistance. Reaching the threshold resistance determines the time to failure for a given device. The time to failure for the open TSV was analyzed and compiled within a compact model, suitable for failure predictions under non-accelerated operating conditions. Assuming a failure is reached, when the resistance increases to double or triple the unvoided metal resistance, a failure will occur after operating for 870 days or 1270 days, respectively, under accelerated conditions, when a current density of 1MA/cm2 is applied.

The demonstrated EM results and simulations provide circuit designers with a useful tool based on TCAD methods to estimate the time-to-failure due to EM of modern interconnect structures. Nevertheless further extensions for EM simulations should be addressed. In future studies the residual stress emerging from the fabrication process, which has a significant impact on the device reliability must be taken into account. Therefore, this stress must also be evaluated and included in the simulations. As this stress is not only dependent on the metal line itself, but also on the surrounding structures and materials, the variability of the material properties has to be considered as well. The influence of the process variability on the device performance is usually modeled using a statistical approach. Furthermore, the micro-structure of the metallization (eg. bamboo structure) and the surrounding interfaces can impact the EM behavior significantly and should be also taken into account.

The impact of the micro-structure, grain boundaries, and interfaces to the surrounding materials are especially pronounced in nano-interconnects. Nano-sized interconnects are connectors between the metal lines and the drains or sources of nano-sized transistors. An approach to model EM in these structures must be examined. The question, if the continuum model implemented in this work is still valid, has to be answered and the EM behavior at grain boundaries and interfaces must be properly addressed. Furthermore, the coefficient is currently treated as a material-dependent, but geometryindependent constant. Due to an increased number of scattering sources, such as at a rough metal interface, will likely need to be adjusted according to the metal thickness or grain sizes.