List of Abbreviations
1  Introduction
 1.1  Motivation
 1.2  Scope of the Thesis
 1.3  Thesis Outline
2  Fundamentals of Memristive Devices and Systems
 2.1  Theory
  2.1.1  Memristor: The Fourth Element
  2.1.2  Memristive Systems
 2.2  Physical Implementation
 2.3  Memristive Device Modeling
3  TiO-Based Memristive Stateful Logic Gates
 3.1  Overview
 3.2  Implication Logic
 3.3  Modeling
  3.3.1  Linear Ionic Drift Memristive Model
  3.3.2  Nonlinear Ionic Drift Memristive Model
 3.4  Simulation Results
 3.5  Summary
4  Spintronic Memristive Stateful Logic Gates
 4.1  Overview
 4.2  Implication Logic Using DW-TMR Memristors
  4.2.1  DW-TMR Memristor
  4.2.2  Domain Wall Dynamics
  4.2.3  DW-TMR-Based Implication Logic
  4.2.4  Simulation Results and Discussion
 4.3  Novel Implication Logic Gates Using STT-MTJs
  4.3.1  Device Principles
  4.3.2  Reliability Modeling and Analysis
   4.3.2.1  Reliable Switching
   4.3.2.2  Modified STT-MTJ SPICE Model
  4.3.3  Improved Implication Logic Gate
 4.4  Reprogrammable Logic Using STT-MTJs
 4.5  Comparison of Improved Implication and Reprogrammable Gates
 4.6  Effect of the MTJ Device Parameters on Reliability
 4.7  Summary
5  Stateful STT-MRAM Arrays for Large-Scale Logic Circuits
 5.1  Overview
 5.2  Implementation of the Reprogrammable Architecture
 5.3  Implementation of the Improved Implication Architecture
  5.3.1  Structural Asymmetry
  5.3.2  Addressing the Asymmetry Issue
 5.4  Complex Logic Functions Using Improved Symmetric Implication
  5.4.1  Non-Volatile Logic Fan-Out
  5.4.2  Stateful STT-MRAM-based Full Adder
 5.5  Toward High Performance STT-MRAM-Based Stateful Logic
  5.5.1  Combined Reprogrammable-Implication Logic
  5.5.2  Parallel STT-MRAM-Based Computation
 5.6  Summary
6  Memristive Charge- and Flux-Based Sensing
 6.1  Overview
 6.2  Memristive Sensing Principles
  6.2.1  Charge-Controlled Memristors
   6.2.1.1  Capacitance Sensing
   6.2.1.2  Power Monitoring
  6.2.2  Flux-Controlled Memristors
   6.2.2.1  Inductance Sensing
   6.2.2.2  Power Monitoring
 6.3  Memristive Devices for Sensing
  6.3.1  TiO-Based Memristors
  6.3.2  Spintronic Memristors
   6.3.2.1  Magnetoresistive Devices
   6.3.2.2  Magnetic Thin-Film Element
  6.3.3  Domain Wall Dynamics
 6.4  Sensitivity
 6.5  Summary
7  Conclusions and Outlook
A  Implication-Based Full Adder
 A.1  NIMP-Based Full Adder
 A.2  IMP-Based Full Adder