List of Figures

• 1.1. Intel MPU transistor density trend starting with the 4040 processor
• 2.1. Processing chain of integrated circuit production
• 2.2. Structure of the semiconductor process flow and its mirror image the TCAD simulation flow
• 2.3. Design flow of a mixed-signal design, comprising of an analog and a digital part
• 2.4. Basic imaging characteristics
• 2.5. Geometric situation in simple projection optical system
• 2.6. Light intensity distribution from a point source projected through a circular imaging lens
• 2.7. RAYLEIGH criterion for resolution of two point images
• 2.8. Expanded flow chart of the wafer fabrication cycle comprising one alignment step and the associated processing
• 2.9. Schematic view of the main components of the illumination system of a lithography tool
• 2.10. General schematic of an ion implantation equipment
• 2.11. An automated parameter tester including wafer prober for final wafer acceptance test
• 2.12. Schematic overview of how the automated parameter tester system performs a test
• 2.13. Example for parameter distributions and resulting $C_p$ and $C_{pk}$ indices
• 2.14. Example for a SPC chart showing a time series of thickness measurements of the gate oxide thickness
• 2.15. Example for a SPC chart showing out-of-control events including the impact of corrective actions for the threshold voltage of a PMOS transistor
• 2.16. The test process
• 2.17. The three phases of IC testing
• 3.1. Schematic time-line of TCAD R&D for device analysis
• 3.2. TCAD work flow scheme showing possible iteration loops
• 3.3. Simple layout example of a PMOS transistor
• 3.4. Typical LOCOS module sequence
• 3.5. Example for proximity effects in a part of an EEPROM cell
• 3.6. Parameter classes for process simulation
• 3.7. Types of process simulation applications
• 3.8. Strategies for re-meshing structures generated by process simulation
• 3.9. Comparison of automatically and manually refined meshes
• 3.10. Comparison of the different meshes in terms of device simulation results
• 3.11. Simple layout example for contact naming of a MOS transistor
• 3.12. Example for a typical input structure for device simulation
• 4.1. Scheme of identified interfaces between TCAD and semiconductor fabrication
• 4.2. Example of a dark field mask configuration
• 4.3. Interface of layout-data to simulation mask-data
• 4.4. Interface of process flow information to process simulation command files
• 4.5. Interface of electrical wafer acceptance test information to device simulation command files
• 5.1. Screen-shot of EXCEL-Sheet description for research&development short-loops or semiconductor processes in development
• 5.2. Conversion scheme for semiconductor process flow information
• 5.3. Electrical test program conversion work-flow
• 5.4. Simulated characteristics of a simulated high voltage PMOS driver compared to SPICE model fit
• 6.1. Doping profile for a 4" diffusion furnace compared to a 8" diffusion furnace before and after optimization
• 6.2. Graphical comparison between the 4" and 8" diffusion recipe for a typical p-well diffusion
• 6.3. Graphical comparison between the 4" and 8" diffusion recipe for a typical n-well diffusion
• 6.4. N-well junction depth over time of annealing step
• 6.5. Examples demonstrating the capabilities of automated process flow documentation
• 6.6. Proximity correction simulation of digital inverter layout
• 6.7. Proximity correction simulation of big digital cell
• 6.8. Comparison of the interconnect shape of a three-dimensional structure of a big digital cell with and without proximity correction
• 6.9. Block diagram of the front-end silicon foundry process flow
• 6.10. Comparison of the three different EEPROM cell architectures
• 6.11. Comparison of simulated and measured tunnel currents through the tunneling oxide
• 6.12. Capacitive equivalent circuit of the EEPROM cell
• 6.13. EEPROM cell after floating-gate mask etch
• 6.14. Structure of the EEPROM memory cell generated by three-dimensional process simulation (one quarter of the cell is shown)
• 6.15. Aerial image simulation result of the floating gate mask of a 3$\times$3 EEPROM cell array
• 6.16. Schematic flow for coupled three-dimensional process and device simulation
• 6.17. Two-dimensional initial structure and resulting three-dimensional mesh after conversion into three dimensions
• 6.18. SC-TOP simulations of Zener diode implantation masks
• 6.19. Generation of Zener diode mesh suitable for device simulation
• 6.20. Comparison of two-dimensional and three-dimensional device simulation results with measured characteristics of PIN-diode
• 6.21. Doping and potential distribution inside the zener structure
• 6.22. Electrical field distribution inside zener structure
• 6.23. Schematic of the Polysilicon fuse measurement
• 6.24. Measured current through fuse and voltage at the fuse terminals as a function of time
• 6.25. Fuse device structure showing the variety of included materials
• 6.26. Comparison of measured and simulated polysilicon fuse resistance as a function of time
• 6.27. Comparison of the simulated temperature and measured polysilicon fuse resistance showing the extracted critical temperature
• 6.28. Temperature distribution in the polysilicon fuse interconnect structure at $\textrm {65 }{\mu }\textrm {s}$ and $\textrm {1.7 V}$
• B.1. A sample CIF ``wire'' statement
• B.2. A sample CIF "polygon" statement
• B.3. The transformations of a CIF "call"
• B.4. EBES raster motion, actual mask making sweeps out 256 rows as it advances horizontally
• B.5. EBES parallelogram example
• B.6. EBES trapezoid types
• C.1. Geometrical situation when biasing a polygon with a given distance
• E.1. Standard geometry of theory of diffraction
• E.2. Viewing angles of source point and projection point as seen from the center of the aperture.
• E.3. Direct light propagation through aperture
• E.4. Coordinate system in a circular aperture
• E.5. AIRY-disk with rings
• E.6. Coordinate system in a rectangular aperture
• E.7. Comparison of different intensity distributions after diffraction at different shapes of aperture