4 Charge accumulation in high temperature processing steps

During the processing of SiC MOSFETs, very high temperatures are necessary to manufacture high-quality devices. This is especially the case for the post-oxidation annealing (POA) of the gate oxide, and the metal contact formation, which require temperatures significantly above 1000 °C. The need for such high processing temperatures is an outstanding difference to the manufacturing process of silicon based devices, where usually much lower temperatures are needed. Furthermore, the requirement for such a high thermal budget may be one reason for the overall poorer interface quality of silicon carbide based devices. Although there are several studies which investigate the impact of various processing temperature and time combinations on the electrical behavior of 4H-SiC capacitors [33, 52], no such work is available for the full manufacturing routes of 4H-SiC MOSFETs, which in general require additional high temperature processing steps. The additional thermal budget during MOSFET manufacturing might in the end result in an increased interface state density due to possible defect generation and/or depassivation of previously passivated states at the SiC/SiO₂ interface.

4.1 Devices and high temperature processing steps

To investigate the impact of each high- processing step on the charge state at the SiC-SiO₂ interface, multiple wafers containing various test structures from an identical processing route were investigated. All wafers were simultaneously subjected to the processing steps with a high thermal budget. After each of these high- processing steps, one wafer was removed from the production line and the capacitance voltage CV curves were extracted using the measurement system described in Section 1.3.1. Since it is not feasible to measure a capacitance voltage curve on the MOSFET test structures without a fully-processed source contact, which is usually manufactured in one of the last processing steps, nMOSCAPs test structures with an area of 2.89 mm² and an oxide thickness of approximately 120 nm were investigated. These MOSCAPs are located on the same wafers as the MOSFETs. Therefore all devices are subjected to an identical thermal budget throughout the entire manufacturing process.

An overview on the investigated high- processing steps is provided in Tab. 4.1 and labeled according to the following scheme:

• • process : post oxidation anneal of the gate oxide (POA),

• • process : deposition of the polycrystalline silicon gate (Poly),

• • process : deposition of the inter-level dielectric (ILD),

• • process : annealing of the inter-level dielectric (Anneal),

• • process to : contact formation at various temperatures.

The complete process chain including all high- steps and the CV measurement is sketched in Fig. 4.1. It is essential to note that the processes to were done in parallel, whereas to are performed in series. Therefore, a sample measured after was subjected to to and but not to , as indicated in Fig. 4.1.

Process	POA	Poly	ILD	Anneal	Contact variations
					800 °C to 1100 °C

It should be pointed out that the post oxidation anneal (POA), which is the first investigated high temperature step (), is the first processing step after oxide deposition. At this point, only a SiO₂ film is present on top of the n-epi layer and no metalization is available for the CV measurement to make contact to the sample. Due to this, the CV measurement after was performed using a mercury probe, which applies mercury contacts with a well-defined area to the sample using a hollow needle. To allow a comparison of the outcome of this measurement with all subsequent ones, which were performed on the polycrystalline Si (poly-Si) contact, the first CV-measurement is corrected for the area of the mercury droplet, and the difference in the work-function between the polycrystalline silicon and the mercury. This correction results in an offset in the gate potential of approximately 0.4 V.