2.2 Investigated devices

All devices produced in-house were fabricated on 4H-SiC n-doped substrates using an industrial process. To analyze the impact of the crystal orientation on the electrical properties, MOSFETs with a lateral and trench design were used. A schematic cross section of the devices is shown in Fig. 1.12 and Fig. 1.13. For the DMOS design (Fig. 1.12), the inversion channel forms on the (0001) crystal plane (referred to as Si-face), wheres for the trench design (Fig. 1.13, left) the channel forms on the () crystal plane (referred to as a-face). All devices received a SiO₂ dielectric deposited via chemical vapor deposition (CVD) and an optimized post oxidation anneal (POA) was done in a NO containing atmosphere for all samples.

To make sure the hysteresis phenomenon is not only a peculiar feature of our devices, a comparison with various SiC power MOSFETs available on the market is given in Section 2.8. The investigated devices were purchased from three different manufactures and randomly labeled A, B, and C to maintain manufacturer anonymity.

In Section 2.6.2, the density of interface states is extracted using charge pumping measurements [82] by using smaller variants of the in-house devices. Therefore, smaller, but otherwise identical MOSFETs with a distinct bulk pad were produced. Here, the Si-face devices have a gate length of 6 µm and a gate width of 100 µm and the a-face devices have a gate length of 0.5 µm and a gate width of 30 µm. All measurements are performed on wafer level using an Agilent B1500A parameter analyzer, an Agilent E5250A switching matrix and an Agilent 4294A impedance analyzer at room temperature unless otherwise stated. Temperature sweeps between −60 °C and 205 °C are performed via an ATT Systems P40 cooling unit. A more detailed description of the measurement system is provided in Section 1.3.1.