Abstract. In the first part of this chapter the threshold voltage instability of commercially available SiC power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress is investigated. It is demonstrated that all SiC-MOSFETs from different manufacturers available on the market show nearly identical voltage shift behavior even under a low-bias operation close to the threshold voltage indicating that the observed instabilities are likely a fundamental physical property of the SiC/SiO₂ system caused by electron trapping in border states which are energetically located close to the conduction band of 4H-SiC.

In the second part of this chapter it is shown that when using JEDEC-like measurement patterns, MOSFETs based on 4H-SiC show amplified voltage shifts during gate bias stress compared to their silicon based counterparts. The majority of the extracted voltage shift originates from fully-reversible components and strongly relies on stress independent measurement conditions such as the reference point for the calculation of the voltage shift and timing parameters. An enhanced bias temperature instability measurement technique using device preconditioning is presented and compared to standard JEDEC-like measurement patterns developed for BTI evaluation of silicon MOSFETs. The proposed preconditioned measurement allows for accurate and nearly delay and recovery time independent extraction of the permanent component within typical industrial timescales. Therefore, the proposed technique allows for a more accurate lifetime prediction of SiC power devices.