2.10 Conclusions

In this chapter, the drain current hysteresis during up- and down-sweeps of the gate voltage in 4H-SiC MOSFETs with the inversion channel either on the Si-face, (0001)-plane, or the a-face, (110)-plane was investigated. The subthreshold drain current of SiC-MOSFETs at a certain gate voltage strongly depends on the preceding gate voltage. A gate voltage sweep from accumulation to inversion results in lower than a gate voltage sweep from inversion to accumulation.

The subthreshold voltage (as defined by (2.1)) may fall below 0 V during up-sweeps depending on the up-sweep starting voltage. For the a-face device, we observe subthreshold voltage shifts up to after an accumulation pulse which corresponds to about 1.4 × 10¹²/cm² trapped charges whereas for Si-face devices we observe an approximately 10 times smaller trap density of 0.1 × 10¹²/cm². Furthermore, it is important to note, that the data-sheet threshold voltage , which is (unlike the subthreshold voltage ) typically measured at much higher drain currents of 1 mA to 10 mA where the channel is much stronger inverted, remains always safely above 0 V. Thus, the normally off characteristics of the SiC-MOSFET are maintained in any switching case despite of the reported hysteresis effect in the subthreshold regime.

The subthreshold voltage shift scales linearly with the extracted from charge pumping measurements, suggesting that deep level interface traps are responsible for the hysteresis. In general, a-face devices show a more pronounced hysteresis due to a higher interface trap density around mid gap, but also higher mobility due to a lower close to the conduction band edge of 4H-SiC. The observed hysteresis is caused by hole capture which occurs for negative gate voltages corresponding to a Fermi level position below the intrinsic Fermi level. Capture and emission times of the holes scale with interface carrier density, which is why hole capture in accumulation and electron capture in inversion occurs within several nanoseconds whereas electron capture in depletion is much slower due to the low free carrier density in the channel at a Fermi level position around midgap. A schematic illustration of the charging/discharging model is provided in Fig. 2.37. Here the interface trap distribution is shown in blue for the Si-face devices and in green for the a-face MOSFETs.

The atomic origin of the sweep hysteresis and the difference in hysteresis for a-face and Si-face 4H-SiC power MOSFETs is suggested to be due to the difference in interface structure and especially the varying density of carbon dangling bonds (P_bC-centers) on both crystal planes, which have been suggested as the origin of the dominant hyperfine EDMR spectrum in SiC based n-channel MOSFETs by Gruber et al. [5, 120] and Cottom et al. [119]. Ion contamination as a cause of the hysteresis is excluded by the sign of the threshold voltage shift, the speed of the capture and emission process and the temperature dependence.

The charging/discharging of the interface during up- and down-sweep does not cause any permanent degradation of the device and also does not show any influence on the reliability. The negative shift caused by an accumulation pulse is fully recoverable via biasing the device subsequently near or above its threshold voltage. Even after several million charging and discharging repetitions, which for example occur during AC-use conditions, no permanent component is observed suggesting fully reversible trapping and detrapping mechanism.