2.3 Gate voltage dependence

We start by analyzing the dependence of the subthreshold voltage on the starting gate voltage (low-level) of the sweep from accumulation to inversion (up-sweep, ). Fig. 2.2 shows the drain current during a gate voltage sweep starting at varying negative gate bias to (up-sweep, blue) and from back to varying negative bias (down-sweep, red) at a drain voltage of 0.1 V. The measurement pattern is sketched in the inset of Fig. 2.2: the down-sweep was performed with a slope of right after the up-sweep with a slope of . While monitoring the gate voltage level at which , , we observe a shift of to more negative gate voltages the more negative the up-sweep starting voltage.

So far, the effect is consistent with negative bias temperature instability (NBTI), which occurs on all MOS technologies, meaning a negative gate stress results in a negative shift of the threshold voltage. However, there are multiple deviations from the typical NBTI behavior regarding the observed hysteresis effect. One of which is the dependence of the subthreshold voltage shift on the up-sweep starting voltage as shown in Fig. 2.3. As long as the up-sweep starting voltage is higher or equal to −3 V, no is observed. Decreasing the up-sweep starting voltage below −3 V leads to a growth of the hysteresis. From this point on, grows linearly with decreasing up-sweep starting voltage until it saturates for gate voltages , meaning any further decrease of the gate voltage does not lead to an increase in . Furthermore, the hysteresis is independent of the high level of the gate pulse as long as it is above the threshold voltage . From the maximum of approximately −4.5 V and (1.8), we extract a density of trapped charges of assuming all charges are captured at the SiC/SiO₂ interface.

The mechanism behind the hysteresis growth becomes more clear by analyzing the CV curves. Fig. 2.4 shows a schematic CV curve (red) with an inset of the hysteresis curve (blue). The hysteresis in the up-sweep emerges as soon as the starting voltage falls below the intrinsic Fermi level (in this case ). As a consequence of the further decreasing gate voltage, the density of holes at the SiC/SiO₂ interface becomes larger than the density of electrons at the interface allowing for hole capture in interface and/or border traps. The process becomes increasingly more efficient until strong accumulation is reached at approximately −15 V and the hysteresis saturates. The explanation of the observed hysteresis by hole capture is consistent with the sign of the threshold voltage shift: a positive charge captured at the interface acts like an additional positive gate potential resulting in a negative threshold voltage shift.

2.3.1 The difference to silicon based devices

There are two reasons why the hysteresis is a feature only observed on SiC based MOSFETs:

• • The first reason is the much larger interface trap density of SiC based devices compared to their silicon based counterparts. For the Si/SiO₂ system typical trap densities are in the range of 10⁹/(eV cm²) to 10¹⁰/(eV cm²) [30, 65]. This is mainly attributed to the very efficient hydrogen anneal used for the interface passivation in silicon based devices [99–103]. For the SiC/SiO₂ system, on the other hand, the aforementioned hydrogenation is not nearly as effective [104–107]. Although there are other passivation gases like nitric oxide (NO), in SiC based devices remains several orders of magnitude higher and is usually in the range of 10¹¹/(eV cm²) to 10¹²/(eV cm²) [86, 108–110].

• • The second reason is the three times larger bandgap of SiC compared to Si. The expected hysteresis is connected to the number of trapped charges at the interface by

  

  with the elementary charge , the vacuum permittivity , the relative permittivity of SiO₂, , the oxide thickness and the total amount of interface charge , which is given by

  

  with the density of interface/border traps within the energetic window . The expected hysteresis can be estimated for both technologies by applying (2.3). Assuming an oxide thickness of approximately 70 nm, which is a typical value for power devices, and a band gap of 1.1 eV for Si, one ends up with an expected hysteresis on silicon devices which ranges from 3 mV to 35 mV. For SiC based devices on the other hand, with a band gap of 3.2 eV, the expected hysteresis ranges from 1 V to 11 V. For simplicity, we assumed and a uniform trap distribution. In reality, and thereby depends on multiple parameters like the Fermi level position during the measurement, trap distributions and the time delay of the measurement as will be discussed in the next sections.