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4.2 Evolution of fixed oxide charges

Fig. 4.2 shows the normalized CV curves after each high temperature processing step given in Tab. 4.1 for 5 n-MOSCAPs from each sample group (wafer). All CV measurement were performed at 30 °C and a frequency of 100 kHz from depletion at −15 V to accumulation at 15 V (up-sweep) and vice versa (down-sweep). With increasing thermal budget, the CV curves shift to more negative voltages. The voltage shift is parallel, which indicates a build-up of fixed positive charges at the SiC/SiO₂ interface. It is important to note that the observed voltage shift is in fact due to the high thermal budget and not caused by the direction of the CV measurement, due to the negligible difference for both sweep directions (not shown).

Figure 4.2: Normalized CV curves extracted from n-MOSCAP test structures at 30 °C and a frequency of 100 kHz after each high- processing step. For each high- step from $P_{1}$ to $P_{54}$ , the flatband voltage shifts up to $\ac {dVfb} \approx \SI {-2.35}{\V }$ to more negative voltages. The extraction level of is indicated as dotted line.

The flatband voltage (math image) extracted from the up- and down- sweep in the data at an extraction level of $0.7 \times C_{\text {max}}$ (dotted line) is depicted in Fig. 4.3. Although $P_1$ is one of the steps with the highest thermal budget ( $\ac {T} >\SI {1000}{\celsius }$ for $\ac {t_ht} >\SI {100}{\min }$ ), the CV curve remains close to the theoretical one (as will be shown in Section 4.2.1). The first shift of the CV curve occurs after $P_2$ , which is the deposition of the polysilicon gate. At this point, (math image) has already shifted by 300 mV. The voltage shift increases with each additional high- processing step to a maximum of approximately 2.35 V after $P_{54}$ . Furthermore, it is important to note that the impact of the gate bias on is negligible ( $< \SI {200}{\milli \V }$ ) compared to the overall voltage shift, which arises due to the thermal budget.

Figure 4.3: Flatband voltage after all high-temperature processing steps. was extracted at the dashed line in Fig. 4.2. arises after the deposition of the poly-Si gate con- tact and increases with each additional processing step with a high thermal budget.

Figure 4.4: Measured CV-curves after the first (POA, $P_1$ ) and the last (Contact 1100 °C, $P_{54}$ ) high- processing step. The CV curve of $P_{54}$ is shifted to more negative gate voltages due to the high thermal budget, which led to a build-up of positive oxide charges. Both curves have been simulated using a total number of oxide charges of 1.0 × 10⁹/cm² for $P_1$ and 4.5 × 10¹¹/cm² for $P_{54}$ . was set to 1.0 × 10⁹/(cm² eV) for both curves.

$ P_1 $ — Figure 4.4: Measured CV-curves after the first (POA, $P_1$ ) and the last (Contact 1100 °C, $P_{54}$ ) high- processing step. The CV curve of $P_{54}$ is shifted to more negative gate voltages due to the high thermal budget, which led to a build-up of positive oxide charges. Both curves have been simulated using a total number of oxide charges of 1.0 × 10⁹/cm² for $P_1$ and 4.5 × 10¹¹/cm² for $P_{54}$ . was set to 1.0 × 10⁹/(cm² eV) for both curves.

4.2.1 Simulated CV curves

Fig. 4.4 shows a comparison of the measured CV curves after $P_1$ (blue) and $P_{54}$ (green), which did show the highest shift, with a simulated CV signal (dashed) of the poly-Si/SiO₂/SiC MOS-System. After $P_1$ , the CV curve is very similar to the ideal curve of the system with a total number of oxide traps (math image) of approximately 1 × 10⁹/cm² (blue). After the last processing step, $P_{54}$ , is shifted to more negative gate voltages due to an increase in trapped positive charges. For the fit, a of approximately $\SI {4.5e11}{\per \centi \metre \squared }$ (green) results in a good agreement with the experimental data. Fig. 4.5 shows the values extracted from the fitting parameters for the complete set of high- (math image) processing steps.

Figure 4.5: Number of positive oxide charges after each high temperature processing step. Af- ter the poly-Si deposition $P_2$ , increases strongly from 1.0 × 10⁹/cm² up to 4.5 × 10¹¹/cm² after $P_{45}$ assuming all charges at the SiC/SiO₂ interface. The high corresponds to a maximum flatband voltage shift of approximately 2.3 V.