3.3 Capacitance-Voltage Profiling (C-V)

In addition to the CP method, the C-V method allows for an energetic profiling of defects as well. The C-V technique was introduced in 1960 in order to determine the majority carrier concentration in semiconductors [113]. Meanwhile, this method is also used for tracking the and shifts in MOSFETs due to previously applied stress [114, 115]. As shown schematically in Figure 3.8, the basic experimental setup can be realized by the application of a bulk voltage () at the drain, bulk and source contacts and a simultaneous measurement of the . The applied signal is a superposition of a DC offset, which drives the MOSFET from accumulation to inversion, and a small AC component with an amplitude typically around 50 mV. Due to the gate capacitance (), the simultaneously measured is phase-shifted as illustrated in Figure 3.9. Using an equivalent circuit diagram can be calculated from the and signals.

Typical curves of with respect to the DC offset of are shown in Figure 3.10. When sweeping the DC component from accumulation to inversion, a depletion layer near the substrate/oxide interface forms because the majority carriers are forced away into the substrate. The remaining fixed ionized acceptors or donors build up a depletion charge and reduce the total gate capacitance. As soon as the minority carriers at the interface exceed the majority carriers and an inversion layer is created, the gate capacitance increases again. From the change of the C-V shape in Figure 3.10 during stress and recovery phases, the different energy levels contributing to degradation and recovery as well as and can be extracted. This allows for a thorough characterization of degradation mechanisms like BTI and HCD.