1.2 Scaling Trend of MOSFETs and Challenges

While decades ago transistor structures were processed in the micrometer range, modern transistor structures have been scaled down to 22 nm in 2008 and to 14 nm or even less in the current generation of transistors [4]. In addition to the scaling of the gate width () and gate length () of the transistors, the oxide thickness () has also been scaled down, reaching values of less than 2 nm, which corresponds in fact to a rather small number of atom layers.

The scaling of the geometry results in several design and fabrication challenges. For example:

• • A short transistor length (less than 100 nm) leads to short-channel effects, e.g., drain-induced barrier lowering, which affects the MOSFET performance. Moreover, channel leakage currents are more pronounced, therefore, the off-current increases significantly

• • Considering that the oxide capacitance () is proportional to the ratio between channel area () and , where , has to be downscaled in the same manner as . Otherwise, would increase significantly which would have a considerable impact on and the switching dynamics. However, is limited to a certain minimum value because of quantum effects like tunneling, leading to a dramatic increase of leakage currents if the oxide thickness is further reduced. With a below this value, a loss-less control cannot be ensured any longer.

• • As a consequence, the oxide electric field () has increased considerably due to the indirect proportionality to . could be decreased by a decrease of . However, due to the limited subthreshold slope, the supply voltages cannot be scaled in the same manner as the device geometry without affecting the ratio between the on- and off-currents. As a consequence, degradation effects depending on , e.g., the bias temperature instability (BTI), have a greater impact in downscaled devices than in devices with thicker oxides.

Another consequence of downscaling is a higher device variability due to the variance of parameters between transistors processed in the same manner. This is because nano-scale devices contain, in contrast to large devices, only a countable number of discrete dopants. Therefore, the slightest deviations of their number or position influence the non-uniform current flow over the width, the so-called percolation path as shown in Figure 1.4 left [3, 5]. Furthermore, the relative deviation of device dimensions due to fabrication variability increases with scaling. As a result of both, the variance of discrete dopants and dimension deviations, even transistors of the same technology and processed in the same manner show a significant variance in their characteristics, like . This variance results in an increased ratio between defective and functional devices and affects the performance of circuits detrimentally [6].

Additionally, any real device contains structural defects, for example, impurities, interstitials, vacancies and dangling bonds. Two of the most important defect types are shown in Figure 1.6, interface defects and oxide defects. While both are considered the main cause of device degradation, oxide defects are the main focus of this thesis. Both have energetic states within the band diagram shown in Figure 1.2 and are capable of exchanging charge carriers with the valance or conduction band of the substrate.

Interface defects occur when interfacing different materials, like crystalline and amorphous . Such material transitions result in an interface region containing trivalent dangling bonds. Such interface states known as -centers, which are amphoteric traps and act as donors as well as acceptors [7, 8]. Typically they act as traps for electrons and holes and distort the device characteristics detrimentally. Charge exchange between interface states and the substrate is consistent with the Shockley-Read-Hall (SRH) theory [9]. In order to ensure a proper MOSFET function, such interface defects have to be reduced considerably. This reduction is realized by a passivation of the dangling bonds by hydrogen () during a processing step of forming gas annealing.

Oxide defects are intrinsic defects and can be either vacancies, e.g., the oxygen vacancy, or bridging atoms, e.g., the bridge. Phenomenologically they are classified in defects near the interface, also called border defects or defects away from the interface [10, 11]. Microscopically the border defects are often associated with ’ centers, which are trivalent silicon dangling bonds in the oxide [8] or hydrogenic defects [12]. Similar to the interface defects, defects in the oxide also can distort device characteristics due to charge exchange events with the substrate. Such charge exchange is consistent with non-radiative multiphonon processes [13–15].

Due to the comparatively large in devices with large , a single capture or emission event caused by an oxide defect has a small impact on the MOSFET parameters. In stark contrast, in nano-scale MOSFETs with dimensions around 100 nm or smaller, containing just a handful of defects such events affect device performance severely [16–18]. Depending on the position of the defect, the percolation path is disturbed as can be seen in the center and right panels of Figure 1.4. Charge exchange events of defects located near or in the percolation path cause a shift, a degradation of the subthreshold slope and a reduction of the on-current as summarized in Figure 1.5. Even one single active defect may shift by a detrimental value, and thus, change the transistors behavior and dynamics in digital circuits dramatically. Such a shift of transistor characteristics can endanger the correct interaction with other components, which makes the circuit less reliable and more likely to fail.