BTI and HCD are among the most important reliability issues in modern devices. However, as already discussed in the previous chapters, these degradation
mechanisms are typically studied in idealized settings. In particular, for BTI studies no voltage is applied to the drain, leading to homogeneous conditions across the oxide and thus to a homogeneous
degradation. As soon as is increased, degradation becomes more and more
inhomogeneous and the contribution of HCD to the total degradation increases (see Subsection 2.3.1). Even though it is well understood that MOSFETs in real circuits are rarely subjected to idealized BTI or HCD conditions, there is only a limited number of studies available on the
impact of the mixed stress conditions as illustrated schematically in Figure 3.1. Therefore, a thorough experimental study of the impact of mixed stress conditions on 2.2 nm
pMOSFETs characteristics of a 130 nm
commercial technology (
−1.5 V and
465 mV) is presented in this chapter, which contains the first
experimental characterization at the single defect level.
As an introduction to this chapter, it should be again mentioned that the permanent component, on the one side, is attributed to the generation of interface and oxide defects, the hopping of through the oxide, and defects with large characteristic emission times. On the other
side, the recoverable component of degradation is typically attributed to the emission events of previously charged oxide defects within experimentally feasible time slots (on the order of seconds or minutes). In the following, the focus
lies mainly on the recoverable component of degradation.
The characterization of recovery in large-area devices (
10 µm,
120 nm or 130 nm) has revealed that with increasing
the recovery can be negligibly small. Figure 5.1 illustrates one measurement in this regard. In this measurement, seven cycles of 5 ks stress and 10 ks recovery at a constant
and each cycle
increasing
were performed.
was extracted from a single
point measurement of
at
(constant voltage
method introduced in Section 3.5). It can be seen that the threshold voltage shift during recovery (
), extracted according Equation 5.1
with
3 ms, reduces with
. For example, the
recovery trace after
−2.8 V (red trace) recovers less than 1 mV in
10 ks.
Figure 5.1: Recovery after mixed NBTI/HC stress: Seven cycles of 5 ks stress and 10 ks recovery at a
constant and increasing
were performed. Top: Recovery traces show
the reduction of
with
. Bottom: Com-
parison of
and a simulation using an electrostatic model. A discrepancy between
and
can be seen, especially at
−2 V.
can be negligibly small (less than 1 mV in 10 ks of recovery) after
mixed NBTI/HC stress. Figure source: [105].
threshold voltage shift | |
recovery time | |
lower limit of the experimental window during recovery | |
upper limit of the experimental window during recovery |
The measurement data are compared to a simulation using an electrostatic model as introduced in Subsection 2.3.1. This model takes into account a lateral position dependent threshold
voltage shift based on a linear approximation of the channel potential under stress according to Equation 2.54. This approximation is valid for lateral positions at the inversion state. At
the pinch-off, the channel potential can be calculated using Equation 2.55. In this regard, it is discussed in Subsection 2.3.1 that using an
electrostatic model, it is expected that recovery is reduced after stress with increasing because drain-side defects most probably will not
contribute to recovery due to the reduced
. However, source-side defects should be
nearly unaffected by
and contribute to
independently from the drain bias.
Although an electrostatic model describes the behavior of after NBTI rather well, Figure 5.1 bottom shows discrepancies between the experimental data and the simulation after mixed NBTI/HC stress. The
measurements summarized in this figure, as well as measurements in [26], indicate that
can be negligibly small after mixed NBTI/HC stress. This would mean that almost no oxide defects contribute to the recoverable component. This contradicts the assumption that source-side defects contribute nearly unaffected to
. Since oxide defects are uniformly distributed all over the device area, such a behavior
cannot be explained by an inhomogeneous
only.
In order to analyze the origin of the discrepancies between the experimental data and the simulation, interplay between NBTI and HCD in large-area devices is
studied. For this, the eMSM measurement method was used according to Section 3.5 and extracted from a single point
measurement of
at
during recovery
(constant voltage method). 58 devices were measured at
130 °C using the following phases:
1. Measure: -
characteristics in the linear (
−0.1 V) and saturation regime (
).
2. Stress: application of a combination within the range of stress conditions
shown in Figure 3.1 per device:
is −1.5 V,
−2 V and −2.5 V,
is 0 V,
−0.5 V, −1 V, −1.5 V, −2 V, −2.5 V and −2.8 V for a certain stress time 0.02 s, 1.11 s and 1111 s.
3. Measure: for
3 ks at recovery conditions (typically
−0.1 V and
).
4. Measure: -
characteristics in the linear and
saturation regime.
From these measurements following was extracted:
• The threshold voltage shift directly after stress (): extracted
as
3 ms
.
• based on the
extraction for
different
.
• during recovery.
• The relative and
extracted from the
-
characteristics.
• Recovery according Equaton 5.1.
Figure 5.2: Degradation after stress: was extracted
at
3 ms. Top: For
20 ms the reduction of
across the gate oxide near the drain re-
gion suppresses NBTI with increasing
. For larger
it can be seen that with increasing
, the interplay between NBTI
and HCD leads to two local minima of
, at
−0.5 V and
−2 V. Center: Similar to the top panel. With increasing stress
time a drift minimum starts to form at
−0.5 V. Bottom: The minimum of
at
−0.5 V forms clearly for
11.1 s and
1.11 ks as discussed in [25, 26]. Figure source: [124].
From Figure 5.2 it can be seen that local degradation minima form after stress depending on the stress voltages and on the stress time. While after
20 ms
decreases or
stays constant with increasing
, for longer stress times
10 s a drift minimum forms
around
−0.5 V. Quite interestingly, for
−1.5 V a second minimum forms at
−2 V. The dependence of the formation of such minima on
is confirmed by the data of
Figure 5.3 for the two cases
−1.5 V and
−2.5 V. Especially for
−1.5 V it can be seen that if
100 s and
0 V,
is always lower than for homogeneous NBTI.
It has already been discussed in literature [25, 26] that drift minima such as shown in Figure 5.2 occur for long stress times. This behavior was explained by competing processes
contributing to the degradation: while sweeping from 0 V to,
e.g., −3 V,
reduces first
due to the fact that
decreases at the drain-side and, as a consequence
fewer drain-side defects capture charge carriers. From a certain
on, this effect is
compensated by the contribution of HCD to
which leads to
an increase. However, this behavior has not been observed for all
and
in the measurement. For example,
reduces at
−1.5 V and
20 ms with increasing
without forming any drift minima. It can be
concluded that whether and where a minimum forms in
depends
strongly on the stress time and on the gate and drain bias.
Figure 5.4: Degradation of the drain current in the linear and saturation regime: While the degradation behavior at
−1.5 V and
1.11 ks is comparable to the results in literature, the curves for
−1.5 V and
11.1 s show that
and
is higher for lower stress times
at certain
combinations. This means that the degradation evo-
lution of both turns around during stress. Similar behavior was also observed for the degradaton of
and
. Figure source: [124].
The analysis of the degradation of and
illustrated in Figure 5.4 shows a strong dependence on
as well. After
−1.5 V and
1.11 ks, a minimum in the
and
curves can be seen around
−1 V, which is comparable to the results in literature [25].
Remarkably, the measurements show that after shorter stress with
11.1 s
and
are higher at a certain
than after stress with
1.11 ks also at
−1.5 V. This means that with increasing stress time both first
increase, then this trend obviously turns around and they decrease again. Such a behavior has not been observed for higher gate bias
−2.5 V in these measurements. For a detailed analysis of the time
dependent
and
evolution at higher gate
stress bias, ten devices were measured using the MSM method (see Section 3.4) with the following phases:
1. Measure: -
characteristics in the linear (
−0.1 V) and saturation regime (
).
2. Stress: application of a combination per device:
is −0.7 V,
−1 V, −1.5 V, −2.0 V, −2.3 V and −2.8 V and
−2.8 V for a certain stress time.
3. Measure: -
characteristics in the linear and
saturation regime.
4. Repeat the second and the third phase with increasing .
5. Relax: application of recovery conditions for .
6. Measure: -
characteristics in the linear and
saturation region.
7. Repeat the fifth and the sixth phase with increasing .
Figure 5.5: Degradation and recovery of the drain current in the linear and in the saturation region as well as the threshold voltage shift: The degradation and recovery were measured
by short interrupts of the stress and recovery phase in order to measure and
. Especially
but also
show a local maximum after
one second of stress, a local minimum after approximately ten seconds of stress, and increases for larger stress times. No turn-around effect was measured for
.
From the -
characteristics
and
are extracted during stress
and recovery, which can be seen in Figure 5.5. It has to be noted that a small discrepancy occurs due to the interruptions of the stress and recovery phase compared to measurements
without interruptions (also mentioned in Section 3.4). This is because each interruption during stress leads to a partial recovery of the degradation and each interruption during
recovery slightly stresses the device. Therefore, the results from these measurements are shown as a schematic illustration but are not suitable as a basis for a further model development. The analysis of the degradation and recovery
of
and
shows that local minima
and maxima occur at higher gate bias as well. Depending on the stress voltage combination,
has a local maximum after
one second of stress, followed by a local minimum after approximately ten seconds of stress.
Such stress-time dependent turn-arounds of degradation have already been observed recently [99, 100, 102] and discussed in Subsection 2.2.6. Although the explanation in the
mentioned subsection cannot be applied to the measured turn-around in the same
way due to the different measurement methods, it gives an idea that II and the interplay of different types of defects together with the creation of secondary generated carriers triggered by II may determine the behavior of device degradation. However, these results merely suggest an interplay between NBTI and HCD and no
detailed information about the particular processes at the single defect level can be extracted from these measurements. Thus, the impact of mixed NBTI/HC stress on
the behavior of single defects was analyzed and the results are presented in the next subsection.