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Abstract
Kurzfassung
1 The Transistor
1.1 The Transistor in Digital Circuits
1.2 Scaling Trend of MOSFETs and Challenges
1.3 Reliability
2 Degradation Mechanisms
2.1 Bias Temperature Instability
2.2 Hot-Carrier Degradation
2.3 Mixed NBTI/HC Conditions
3 Experimental Characterization
3.1 On-The-Fly (OTF) Measurements
3.2 Charge Pumping (CP)
3.3 Capacitance-Voltage Profiling (C-V)
3.4 Measure-Stress-Measure (MSM)
3.5 Extended Measure-Stress-Measure (eMSM)
3.6 Random Telegraph Noise (RTN) Analysis
3.7 Time-Dependent Defect Spectroscopy (TDDS)
3.8 Temperature Accelerated Measurements
3.9 Conclusions
4 Discrete Steps in Large-Area Devices
4.1 Probability to Measure Discrete Steps
4.2 Experimental Characterization
4.3 Conclusions
5 Impact of Mixed NBTI/HC Stress on MOSFET Characteristics
5.1 Large-Area pMOSFET Characteristics
5.2 Individual Defects
5.3 Volatile Oxide Defects
5.4 Conclusions
6 Conclusion and Outlook
A List of Symbols
A.1 Physical Constants
A.2 Physical Quantities
A.3 Acronyms
List of Figures
List of Tables
Bibliography
5.1 Relative lateral defect position and classification due to capture behavior: By exploiting the recovery drain bias dependence of the step heights for constant gate recovery voltage , the lateral position (0 at source, 1 at drain) was extracted [105]. The uncertainty of is about 20 %. Defects A3, B3, B4 and C2 showed a very complex behavior (e.g., due to an overlap with other defects in the spectral map at certain bias conditions) and were not characterized fully. The defects are assigned to three types according to their capture behavior during mixed NBTI/HC stress which is explained based on Figure 5.9.
5.2 Defect volatility after different stress conditions: Summary of the observed defect volatility. While the defects B3 and B4 showed a regular volatile behavior by getting inactive and active again from time to time, the defects B1, C1, C2 and C3 were volatile after all stress conditions.