5. Applications

GATE LEAKAGE is one of the most important issues for contemporary CMOS devices. Based on the tunneling models outlined in Section 3 two different application areas will be investigated in this section. First, gate leakage in contemporary MOS transistors will be studied and compared to measurements. Emphasis is put on the distinction between the different sources of the tunneling current, namely the region below the gate and the region near the drain and source extensions.

Device engineers commonly rely on gate leakage measurements of turned-off devices to evaluate the power consumption of CMOS circuits. This may lead to erroneous results since for turned-on devices, hot-carrier tunneling prevails which may exceed the turned-off tunneling current. Models which are based on simplified assumptions of the carrier energy distribution function fail to predict gate leakage in such cases.

Advanced CMOS devices will use alternative dielectric materials as gate dielectrics. However, a pronounced trade-off between the height of the energy barrier and the dielectric permittivity exists. This makes the use of optimization necessary to find the optimum layer composition. Furthermore, alternative dielectrics are not ideal insulators but contain defects which give rise to trap-assisted tunneling. As a state-of-the-art example, tunneling in ZrO$_2$-based MOS capacitors will be studied and compared to measurements.

As a second important application area, non-volatile memories will be studied. Unlike MOS transistors, non-volatile memory devices represent an application where tunneling is not a spurious effect, but crucial for the device functionality. After a short review of non-volatile memory technology, the tunneling current of conventional EEPROMs and advanced structures will be studied. In contrast to these devices SONOS (silicon-oxide-nitride-oxide-silicon) EEPROM devices store the charge not on an isolated contact, but in a layer of trap-rich dielectric.

Recent efforts to reduce the charging time of non-volatile memory devices resulted in multi-barrier tunneling devices and EEPROMs with asymmetrically layered tunnel dielectrics. The operation of these devices will briefly be described at the end of this chapter.

Subsections

• 5.1 Tunneling in MOS Transistors
  • 5.1.1 Tunneling Paths in MOS Transistors
  • 5.1.2 Channel Tunneling
    • 5.1.2.1 Effect of the Polysilicon Gate Doping on the Channel Tunneling
    • 5.1.2.2 Effect of the Substrate Doping on the Channel Tunneling
    • 5.1.2.3 Effect of the Dielectric Thickness on the Channel Tunneling
    • 5.1.2.4 Effect of the Barrier Height on the Channel Tunneling
    • 5.1.2.5 Effect of the Carrier Mass on the Channel Tunneling
    • 5.1.2.6 Effect of the Dielectric Permittivity on the Channel Tunneling
    • 5.1.2.7 Effect of the Lattice Temperature on the Channel Tunneling
    • 5.1.2.8 Comparison to Measurements
    • 5.1.2.9 Validity of Compact Models
  • 5.1.3 Source and Drain Extension Tunneling
    • 5.1.3.1 Effect of the Polysilicon Gate Doping on the Source and Drain Extension Tunneling
    • 5.1.3.2 Effect of the Substrate Doping on the Source and Drain Extension Tunneling
    • 5.1.3.3 Effect of the Dielectric Permittivity on the Source and Drain Extension Tunneling
    • 5.1.3.4 Effect of the Lattice Temperature on the Source and Drain Extension Tunneling
  • 5.1.4 Hot-Carrier Tunneling in MOS Transistors
  • 5.1.5 Alternative Dielectrics for MOS Transistors
  • 5.1.6 Trap-Assisted Tunneling in ZrO$_2$ Dielectrics
  
  
• 5.2 Tunneling in Non-Volatile Memory Devices
  • 5.2.1 Conventional EEPROM Devices
    • 5.2.1.1 Static SILC in EEPROMs
    • 5.2.1.2 Transient SILC in EEPROMs
  • 5.2.2 Alternative Non-Volatile Memory Devices
    • 5.2.2.1 Non-Volatile Memory Devices Based on Trap-Rich Dielectrics
    • 5.2.2.2 Multi-Barrier Tunneling Devices
    • 5.2.2.3 Non-Volatile Memory Devices Based on Crested Barriers

A. Gehring: Simulation of Tunneling in Semiconductor Devices