D I S S E R T A T I O N

About Single-Electron Devices and Circuits

ausgeführt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften
eingereicht an der Technischen Universität Wien
Fakultät für Elektrotechnik

von

Christoph Wasshuber

Favoritenstr. 89/2/11,
A-1100 Wien
Matr.-Nr. 8725919
geboren am 23. Mai 1968, in Wien.

Wien, im Jänner 1997

 

• Kurzfassung
• Abstract
• Acknowledgments
• List of Symbols
  • Units
  • Variables and Fundamental Constants
  • Graphic Symbols
• Definition of Terms and Abbreviations
• Material Properties
• 1 Introduction: What is Single Electronics?
• 2 Theory of Single Electron Tunneling
  • 2.1 Characteristic Energies
    • 2.1.1 Electron Electron Interaction
    • 2.1.2 Quantum Confinement Energies
  • 2.2 Work Done by Voltage Sources
  • 2.3 Helmholtz's Free Energy
  • 2.4 Tunneling
    • 2.4.1 Transmission Probability
    • 2.4.2 Tunnel Rate
  • 2.5 Minimum Tunnel Resistance for Single Electron Charging
  • 2.6 Influence of the Electromagnetic Environment
  • 2.7 The Double Tunnel Junction
  • 2.8 Single Electron Transistor
  • 2.9 Co Tunneling
  • 2.10 Summary
• 3 Simulation of Single Electron Devices
  • 3.1 Free Energy of an Arbitrary Circuit
    • 3.1.1 Notation
    • 3.1.2 Electrostatic Energy
      • Voltage-Controlled Voltage Sources
      • Current Sources
    • 3.1.3 Work of Voltage Sources
    • 3.1.4 Free Energy
    • 3.1.5 Method of Critical Voltage
  • 3.2 Tunneling: a Stochastic Process
  • 3.3 Master Equation Method
    • 3.3.1 Krylov Subspace Approximate of the Matrix Exponential Operator
  • 3.4 Monte Carlo Method
  • 3.5 Comparison between Master Equation and Monte Carlo Method
  • 3.6 Combination of Monte Carlo Method with Direct Calculation
• 4 Implementation Issues
  • 4.1 Summary of the Equations Describing SET Devices
  • 4.2 Code structure
    • 4.2.1 Graphical User Interface
    • 4.2.2 Flow Chart
    • 4.2.3 Random Number Generator
      • Step Size
    • 4.2.4 Accelerating the Simulator
• 5 Applications
  • 5.1 Fabrication Techniques
    • 5.1.1 Shadow Mask Evaporation
    • 5.1.2 Step Edge Cut Off
    • 5.1.3 Planar Quantum Dots
    • 5.1.4 Poly Silicon Structures
    • 5.1.5 Gold Clusters
  • 5.2 Single Electron Memories
    • 5.2.1 Operation Temperature
    • 5.2.2 Error Rate/Probability
      • Bit Errors
      • Read/Write Errors and Access Time
    • 5.2.3 Random Background Charge
    • 5.2.4 Power Consumption
    • 5.2.5 Manufacturability
    • 5.2.6 Single Electron Flip Flop
    • 5.2.7 Multi Tunnel Junction Memory
    • 5.2.8 Ring Memory
    • 5.2.9 Qo Independent Memory
    • 5.2.10 Multi Island Memory
    • 5.2.11 Discussion of Simulation Results
• 6 Outlook
  • 6.1 Fabrication
  • 6.2 Application
  • 6.3 Simulation
• A Capacitance Calculations
  • A.1 Self Capacitance of a Sphere
  • A.2 Self Capacitance of a Sphere with a Dielectric Shell
  • A.3 Capacitance of Two Spheres
  • A.4 Capacitance of an Arbitrary Arrangement of Spheres
• B Fermi Energy Dependence on Free Charge Carrier Concentration
• C Solutions to Schrödinger's Equation
  • C.1 The Infinite Potential Well
  • C.2 The Finite Potential Well
  • C.3 The Rectangular Potential Barrier
• D Integration of Fermi Functions
• E Fermi's Golden Rule
• F Second Order Co Tunneling Rate at Zero Temperature
• G Rational Padé Approximations
• H Arnoldi Algorithm
• Bibliography
• Publications
• Index
• Curriculum Vitae