Abstract

Device degradation and gate oxide reliability has become more and more important in modern semiconductor industry because the challenges for devices increase with miniaturization, larger stress within the circuit, and due to innovative technologies. Besides the reliability of mechanical soldering and wiring, it is of considerable importance to protect the transistor already in the early stages of processing from environmental impurities and mechanical stress. To furthermore guarantee the switching of high currents with minimum power dissipation as well as short-circuit stability, different isolation and metalization layers are deposited in a specific composition and sequence on the active areas of the transistor at the end of device fabrication (back-end of line). It is an accepted fact that different passivation concepts and layer sequences affect the electric characteristics and the reliability of silicon devices, because a lot of hydrogen is incorporated into the system during the back-end process. It is assumed that high temperatures going along with layer deposition and annealing support hydrogen diffusion toward the gate oxide where it may passivate defects within the oxide and at the interface. When subjecting the device afterwards to electrical and thermal stress, the hydrogen may be released again, thereby re-activating previously passivated defects.

Just like any semiconductor manufacturer worldwide, Infineon Villach has repeatedly encountered the problem in the past, and although particular solutions to some technologies have already been found, a global understanding of the underlying physics behind the interplay of processing and degradation is lacking. Because it is likely that new problems with the same roots may become relevant in future technology development, it is of fundamental importance to develop a physically based model which is able to link defect generation and passivation to single process steps.

Besides the above mentioned process impacts, also the physics behind the degradation mechanisms of gate oxide and interface are far from being understood. One of the most important degradation mechanisms is the so-called ‘Negative Bias Temperature Instability’ (NBTI) which leads to time dependent threshold voltage shifts when the gate oxide of the device is stressed at an elevated temperature and bias. NBTI is particularly interesting for the back-end process since it is assumed that the degradation mechanism is closely connected to hydrogen passivation of the Si–SiO interface.

One aim of this PhD thesis is to investigate the role of hydrogen in NBTI and to verify the results by means of process splits. Specific emphasis is put on high voltage (HV) MOSFET devices having 30 SiO gate oxides, as processed at Infineon Villach. Until now the scientific community has mainly been focusing on ultrathin (nitrided or high–) oxides whereas contributions on thicker oxides relevant for power technologies are hardly found in literature.

At first, basic signatures of the ‘Bias Temperature Instability’ (BTI) of 30 SiO devices are collected using common measurement methods and the results are compared to state-of-the-art thinoxide high– technologies. This preliminary study contains considerations on electrostatics and dynamics of degradation and recovery and helps to collect fundamental electric characteristics of emerging defects. A literature study on the current understanding of different species of point defects and their correlation to hydrogen is presented in order to enhance the physical understanding. The collected results are used to develop new measurements setups and experimental procedures which enable us to characterize threshold voltage shifts in various ways and assign the different contributions to certain defect classes with particular attributes. From the data and conclusions a microscopic degradation model is going to be suggested which is capable of explaining (at least qualitatively) the obtained results. In order to include hydrogen, the new measurement routines are performed on different split wafers which provide demonstrably different hydrogen budgets within the gate oxide. The results are cross-checked with the predictions of the suggested microscopic degradation model, agreements are highlighted and conclusions are drawn on the process impact.

The current microscopic model explains device degradation under NBTI as a two stage process, the precursor being an oxygen vacancy defect in the amorphous SiO gate oxide. By subjecting the device to thermal and electrical stress (NBTI) the bond may be broken, thereby creating a positively charged defect. This defect is independent of hydrogen, rechargeable and can be annealed, provided it has been neutralized in advance. The second defect class consists of interface states (dangling bonds) which are created due to field- and temperature-assisted release of hydrogen. Studies suggest that the released hydrogen may become trapped in the broken oxygen vacancy, thereby blocking the relaxation of the oxide defect. These quasi-permanent defects play an important role for the NBTI-stability of a technology since they recover just slowly and only under certain conditions, and due to their correlation to hydrogen, their concentration depends strongly on the back-end process.