1 The Negative Bias Temperature Instability

1.1 Industrial Background and Motivation

Once a new device technology is released from product line, it has to overcome several qualification procedures before it finally gets approved for delivery to the customer. Within those qualification tests it is checked for example whether the new product is working regularly and whether it meets the proposed parameter specifications. Besides initial parameter testing, also the reliability of random samples is monitored meticulously during different stages of the fabrication (i.e. wafer level, package level). This is done in order to collect statistics about extrinsic defect densities causing early device failure and parameter drifts causing gradual degradation of the device within years under operating conditions. Furthermore, fundamental conclusions are drawn on process changes which go along with device shrinking and upgraded innovation standards. Companies invest a lot of money and man power in this area to develop, produce, monitor and evaluate reliability test chips on split wafers that are specifically designed for gaining experience in process influences helping to optimize device performance while simultaneously minimizing production costs. Hence, physically based models explaining process influences on device performance are highly demanded and of great economical interest.

During reliability testing every important device parameter is assigned to a certain drift margin which has to be satisfied and finally determines the lifetime of the product. Considering that the aimed lifetimes of most semiconductor products lie in the range of several tens of years whereas a single qualification test has to be completed within hours, it would be highly inefficient and much too time consuming (if not impossible) to perform lifetime prediction tests under use conditions. Thus, in order to guarantee within a reasonable testing time that an airbag chip will still work at the end of the cars’ lifetime, it is necessary to subject devices to extreme test conditions (accelerated tests). For the analysis of the data, elaborated acceleration models are required allowing to estimate the actual parameter drift under use conditions from a parameter shift measured under accelerated conditions. Thus, in order to make reliable lifetime predictions, physically based acceleration models are urgently needed for each degradation mechanism. So far most existing models are empirical.

One of the most popular degradation mechanism affecting the gate oxide and the interface of metal oxide semiconductor field effect transistors (MOSFETs) is the so-called negative bias temperature instability (NBTI). As opposed to destructive failure modes like time dependent dielectric breakdown (TDDB), NBTI does not cause hard failures (short circuits across the oxide) which limit the possibilities of post stress characterization dramatically but rather leads to a creeping shift in the threshold voltage (typically several tens of ) and to a gradual degradation of the channel mobility and the transconductance of a conventional metal oxide semiconductor (MOS) transistor. The resulting variations in the analog transfer characteristics of the device can cause severe problems especially when the afflicted transistor is incorporated in a digital network or when the demanded specification margin of the technology is very narrow. Since NBTI is very sensitive to variations in device processing, it is particularly hard to control the NBTI resistivity of a technology during device development. The main focus of this PhD thesis is to broaden the knowledge around NBTI by performing stress/recovery experiments on specifically designed test chips. Furthermore, correlations of the effect with process influences, in particular with hydrogen introduced during the back-end of line (BEOL) fabrication, are studied extensively by means of wafer splits produced at Infineon Technologies Austria.