2.2 Classification of defect charges by their electrical response time

When neglecting the spurious shift caused by increased Coulomb scattering, the true reliability concern linked to negative bias temperature instability is originated in defects representing electrically active charges which counterbalance the applied gate potential causing a Fermi level dependent threshold voltage shift in the subthreshold region of the device. Besides their physical origin which will be discussed in detail in Chapter 4, defect charges may be classified empirically by their electrical response time, in particular, by their ability to communicate with the silicon substrate, thereby changing their charge state.

A very basic experimental classification of defect charges may differentiate between interface states and oxide traps, the first exchanging carriers with the silicon substrate very rapidly according to SRH theory, the latter being either permanently charged or provide at least carrier exchange time constants which are slow enough so that their capture and emission processes may be observed in low frequency or DC experiments as well. Naturally, such a classification is physically not well defined since the distinction is directly linked to a particular experimental setup. On the other hand, the differentiation of defects classes by their experimental response time seems obvious and reasonable not at least because their time and bias dependent appearance directly reflects their influence on device reliability under certain operating conditions.

To develop a basic understanding of the relative contributions of different defect types to the overall defect charge dependent threshold voltage shift, the basic experimental approach is usually to combine the results of a DC experiment being sensitive to both fast and slow states with the results of an AC experiment being sensitive only to fast interacting defects like for example interface states. The DC component is basically represented by the threshold voltage shift calculated from the drain current degradation before and after NBTI stress (as discussed in Section 2.1). The shift around the threshold voltage of the device combines the relative charge contributions of all kinds of defects located within the oxide and at the SiO/Si interface.

2.2.1 Charge pumping as a qualification tool

In order to investigate the contribution of fast interface states separately, additional methods have to be applied since a DC measurement is by far not fast enough to capture the fast recombination time constants associated with interface state charging. A well developed technique allowing to count the total number of interface states within a defined energy range of the silicon bandgap is the so-called charge pumping (CP) method [36, 37]. During CP, the gate junction is pulsed continuously between inversion and accumulation using a trapezoidal pulse shape and frequencies typically between 1 and 1. The source and the drain junction of the transistor are short-circuited during the measurement acting as minority carrier sources during the inversion phase of the gate pulse. The source/substrate and drain/substrate diodes of the MOSFET structure are typically slightly reverse biased in order to suppress geometric leakage currents appearing at high gate pulsing frequencies [38, 39]. During the accumulation phase of the gate pulse the substrate junction (typically held at 0.0 during the measurement) provides a source of majority carriers.

CP is a dynamic measurement method which drives the interface periodically into a non-steady state by switching the gate bias quickly between inversion and accumulation. In inversion, minority carriers coming from the highly doped source/drain junctions get trapped in interface states located energetically within the silicon bandgap, while during the subsequent accumulation phase, majority carriers coming from the silicon substrate recombine with previously trapped inversion charges giving rise to a DC substrate current () which is proportional to the average density of interface traps () within a defined energy range (). Hence, from an experimental point of view, we denote each trap fast enough to contribute to the charge pumping signal within half of a gate pulsing period as an interface state. This approximation is not too bad according to elastic tunneling simulations of Heh et al. [40] who calculated a spatial probing depth of approximately 5–6 Å in pure amorphous SiO using high/low times of 1 which corresponds to a frequency of 500.

Following [37], the maximum CP current is given by

where is the elementary charge, is the effective gate area and is the gate pulsing frequency. The effective gate area defines the region below the gate oxide where trapping and detrapping may occur. It is generally smaller than the geometric gate area due to space charge regions which emerge when applying a reverse bias to the source/drain junctions. The pumped charge per area () and pulse period is calculated by dividing the maximum CP current by the effective gate area and the pulse frequency:

where is the number of pumped charges per area and pulse period.

The upper () and lower () boundary of the active energy interval may be derived from the equations of the SRH theory, yielding

where is the gate pulse amplitude (), and are the thermal drift velocities of holes and electrons, and are the capture cross sections for electron and hole capture, is the intrinsic carrier concentration, and are the fall and rise times of the trapezoidal gate pulse and and are the charge pumping threshold and flat band voltages.

From Eq. 2.33 and Eq. 2.34, the scanned energy interval may be calculated as

where the particular thermal drift velocities and capture cross sections for holes and electrons have been replaced by their average values and .

Following [41], the thermal drift velocity in Eq. 2.35 can be approximated as

where is the effective mass of the particular carrier. The experimental determination of the capture cross section is typically performed using three level charge pumping [42, 43], deep level transient spectroscopy (DLTS) [44, 45], capacitance voltage (CV) sweeps [46] or from conductance measurements [47]. Although the capture cross sections reported in literature vary considerably dependent on the technique with which they have been determined, most authors report values between and , the larger values corresponding typically to defect states located energetically close to midgap, the smaller values are often associated with trap levels located closer to the band edges. Some authors, i.e. [48], report that the capture cross sections of interface traps can may be considered as constant over a wide temperature and energy range.

Following [41], the temperature dependent intrinsic carrier concentration is given by

where is the effective density of states in the conduction band and is the effective density of states in the valence band.

In order to calculate the active energy interval for a particular device and different experimental setups, the charge pumping related threshold and flatband voltages have to be determined experimentally from constant base level and constant high level charge pumping measurements. The method is described in detail in [49]. Fig. 2.7 (a) shows constant base level () and constant high level () charge pumping measurements performed on a PMOS device (SM5P/30/H2) measured with a source/drain to substrate reverse bias of -0.2 at a temperature of 20 °C. The charge pumping related threshold voltage corresponds to the gate voltage at which the slope of the curve has its maximum (numerical derivative illustrated by open triangles), the charge pumping related flatband voltage corresponds to the gate voltage at which the slope of the curve has its maximum (numerical deviation illustrated by open diamonds). The same procedure has been performed for different temperatures ranging from -50 °C to 140 °C and the results for and are illustrated in Fig. 2.7 (b) showing that the difference between and shrinks with increasing temperature. This is due to the fact that the intrinsic carrier concentration (cf. Eq. 2.37) increases exponentially with the temperature, providing at higher temperatures a sufficiently large carrier concentration for trap filling already in weaker inversion, and accumulation, respectively.

When inserting the thermal drift velocities (Eq. 2.36) and intrinsic carrier densities (Eq. 2.37) as well as the measured charge pumping threshold and flatband voltages into Eq. 2.33 and Eq. 2.34, we may calculate the charge pumping emission boundaries and for different experimental setups as a function of the temperature. The results for three different rising/falling slopes of the gate pulse ranging from to are illustrated in Fig. 2.8 (a) assuming a medium capture cross section of = . The result demonstrates that the emission boundaries approach the band edges with lowering the measurement temperature (due to ) and with steeper rise and fall edges of the gate pulses. In particular, when measuring at -50 °C using rising/falling slopes of , the detectable energy interval covers nearly the entire silicon bandgap, the emission boundaries being then only about away from the silicon band edges. When measuring at higher temperatures using less steep rising/falling slopes, the active energy range becomes continuously narrower mapping then only a very small area around midgap. The development of being symmetrically around midgap when using a symmetrical pulse shape, is illustrated as a function of temperature in Fig. 2.8 (b).

2.2.2 Energetic mismatch between the CP technique and the static DC approach

When applying charge pumping in order to estimate the interface state dependent contribution to the drain current degradation measured under DC bias conditions, it is necessary to convert the stress induced increase of the CP current () as well as the stress induced increase of the pumped charge (), correctly into a corresponding interface state dependent threshold voltage shift (). The conversion is generally not straight-forward if the energy interval of charged defects under DC bias conditions (cf. in Eq. 2.25) does not coincide with the active energy interval profiled during charge pumping (cf. in Eq. 2.35). The situation is illustrated schematically in Fig. 2.9 (a) where is depicted on the left hand side and is illustrated on the right hand side. The energy interval may be adjusted experimentally by varying the shape of the gate pulse and the temperature. In particular, is independent of the charge state of the interface traps and generally contains information about parts of both the upper and lower half of the silicon bandgap when using a symmetrical pulse shape. By contrast, when measuring the drain current at a constant gate bias, and the obtained threshold voltage shift are governed by the current Fermi level position during read-out and by the net charge state of electrically active interface states, cf. Eq. 2.25.

Fig. 2.9 (a) suggests that a reliable comparison of the charge pumping signal and the DC drain current measurement can only be achieved when taking the energetic mismatch either quantitatively into account (i.e. by a weight factor) or alternatively when tuning both measurement techniques in way so that their energy intervals overlap.

Assuming a homogeneous distribution of interface traps across the entire silicon bandgap, we may consider the energy mismatch illustrated in Fig. 2.9 (a) by means of a weight factor ():

Assuming the PMOS transistor is biased at its physical threshold voltage (cf. Eq. 2.4), the Fermi level position may be approximated as

yielding for at the threshold voltage

From Eq. 2.35 and Eq. 2.40 we may derive an analytic expression for the weight factor at the threshold voltage of the device:

In Fig. 2.9 (b) the weight factor is plotted as a function of the temperature for three different rising/falling slopes.

It has to be pointed out that the weight factor approach implies that the distribution of interface states within the silicon bandgap is uniform. As will be discussed in Chapter 4, this is a very crude approximation since real density of state profiles have rather a U-shape which is more or less symmetrically around midgap [50]. In particular, when and are significantly misaligned, the weight factor approach may introduce a large error due to the non-uniformity of the DOS profile.

The best way allowing a reliable conversion without making any assumptions on the density of state profile is to align and in advance. By combining the results of Eq. 2.34 and Eq. 2.39, we may derive an appropriate specification for the rising slope of the gate pulse in order to make the lower emission boundary () coinciding with the Fermi level position at the threshold voltage ():

We may derive a second specification for the falling slope of the gate pulse in order to adjust the upper emission boundary () to the amphoteric transition level of the interface states which is assumed to be :

The calculated rising and falling slopes leading to a 100 overlap of and at the threshold voltage of the device are illustarted in Fig. 2.10 (a) as a function of the temperature. In Fig. 2.10 (b), the corresponding rise and fall times have been calculated assuming a pulse amplitude of 1. According to Fig. 2.10, a 100 overlap would require a considerable assymetric pulse shape, the rising slope being much steeper than the falling slope. In principle, such a pulse shape can be generated by a conventional pulse generator, however, due to the large fall time, the pulsing frequency would become too small in order to achieve a reasonable measurement resolution of the maximum charge pumping current (cf. Eq. 2.31) making the measurement procedure unfeasible on MOS devices having typical device geometries.

A reasonable compromise between the weight factor approach and the unfeasible 100 overlap may be achieved by assuming a symmetrical density of state profile of interface traps around midgap. When doing so, we can use a symetrical pulse setup again, the rising and falling slopes being adjusted to make the lower emission boundary coinciding with the Fermi level position which guarantees at least that the whole range of is covered by . Considering further that a comparable energy range in the upper half of silicon bandgap is profiled, the weight factor becomes 1/2. Thus, except for the symmetry assumption, no additional approximation on the shape of the density of state profile has to be made in order to accomplish the conversion from to which is a considerable improvement in comparison to the uncorrelated weight factor approach.