3.3 Duty cycle dependence of NBTI degradation

As indicated in the previous chapter, recovery leads to less severe device degradation under AC operation compared to DC operation. This considerably prolongs the lifetime of MOSFETs in digital circuits where the conventional static NBTI stress may lead to a significant underestimation of the NBTI lifetime [66, 67, 68]. In literature, the recovery effect occurring during the stress interruption phases is either attributed to interface state passivation [66] or to hole emission from previously charged oxide defects [8]. For instance, Chen et al. [66, 69] assumes that during stress, the interface acts as a hydrogen source injecting hydrogen from Si–H bonds into the oxide after bond distortion while during recovery the interface acts as a hydrogen sink recapturing hydrogen which diffuses immediately back to the interface after terminating stress. Following [70], the power-law exponent is reported to be lower for AC than for DC operation at least at sufficient large stress times.

The dynamic NBTI effect was found to depend on temperature and gate oxide thickness but not on the stress frequency. The frequency independence was confirmed by several studies for the following band widths: 0.5 – 100 by [69]; 2 – 20 by [70]; 1 – 2 by [71]; 10 – 2 by [72].

As opposed to the pulsing frequency, the gate voltage duty cycle (‘ON time’ divided by ‘total time’) is reported to considerably influence the observed amount of degradation at the end of stress [70, 71, 72]. Most studies report a monotonic evolution of the degradation, with an apparent plateau around a duty cycle of 50.

In order to investigate the duty cycle dependence of NBTI, several PMOS devices (SM6P/30/H1) were stressed at a frequency of 1 for 100 (100,000 pulses) at 125 °C with variable duty cycle ranging from 0.1 to 100, cf. Fig. 3.8 (open symbols). During AC stress, the gate junction was pulsed between 0.0 and -20.0 corresponding to an effective oxide field of approximately 6.3 during the high phase of the gate pulses. During read-out, the gate junction was pulsed at a frequency of 500 (rising/falling slopes 20; duty cycle 50) between +2.0 and -2.0 in order to record the maximum CP current. Immediatly after terminating stress, the maximum CP current was monitored with a minimum stress-measure delay of 40, cf. Fig. 3.8 (a) (open diamonds). Subsequently to the CP measurement (total duration 1), the degradation was recorded by monitoring the degraded drain current at -1.1 corresponding approximately to the threshold voltage of the device, cf. Fig. 3.8 (b) (open triangles). Note that the effective stress time in seconds () reflects the duty cycle in when stressing the device for 100 under AC bias conditions, cf. Eq. 3.7.

As can be seen in Fig. 3.8 (a) and (b), as a function of the duty cycle both the CP current and the shift show a ‘S’-like curve shape with a steep increase at low duty cycles (0.1 – 10), a monotonic development at intermediate duty cycles (10 – 90) and another steep increase at high duty cycles (90 – 100). The results agree with the study of Fernández et al. [71] who applied AC stress pulses with a frequency of 10 to 1.4 silicon oxynitride (SiON) gate dielectrics and with the results of Huard et al. [72] who applied a stress pulsing frequency of 100 to 1.7 plasma nitrided oxide (PNO) gate dielectrics. Both referenced authors performed their experiments at 125 °C as well.

The first increase at low duty cycles in Fig. 3.8 (a) and (b) may be explained by the sharply rising effective stress times. The second increase at high duty cycles cannot be explained by this argument since the effective stress time changes only by 10 when applying AC stress with duty cycles between 90 and 100. On the other hand, when increasing the duty cycle, the effective relaxation periods between the stress intervals decrease, providing less time for recovery during the repated stress interruption phases. Hence, the appearance of the second increase suggests that it is important whether the entire stress phase is applied completely uninterrupted (DC) or interrupted (AC).

To elaborate this assumption in more detail, a second set of measurements was performed, where we have stressed separate PMOS devices having the same geometry for an ‘equivalent’ DC stress time. For example, stressing a device under AC bias conditions for 100 using a duty cycle of 10 correponds to an effective stress time of 10 which is compared in the following to a 10 lasting DC stress experiment. The results gained from these ‘equivalent’ DC experiments are illustrated as full symbols in Fig. 3.8 (a) and (b). When comparing the AC stress runs to the DC stress runs applied for the same effective stress times, a hysteresis emerges, representing a reduced degradation as a consequence of stress interruption and possibly involved recovery. Note that not before the recovery periods fall below 10 (duty cycle 99) the hysteresis disappears, giving then similar results as during DC stress. The experiment demostrates that interrupting the stress phase by only 10 or even less is already sufficient to influence the degradation dynamics considerably, which is consistent with the observation that OFIT is afflicted with recovery even when using a 2 pulsing frequency, cf. Fig. 3.5.

Note that the CP results (cf. Fig. 3.8 (a)) agree very well with the shifts (cf. Fig. 3.8 (b)) calculated from the drain current degradation (they are proportional) indicating a strong correlation between interface state creation and threshold voltage shift. Whether the obtained threshold voltage shifts can be explained completely by the existence of charged interface traps remains an open question which is going to be addressed in the following chapters.

In order to study the influence of the stress interruption time () on degradation and recovery dynamics, we have performed additional AC stress experiments on different devices at 125 °C. In this particular set of experiments we keep the low level recovery times () of the gate pulses (0.0) constant, while the high level stress times () of the gate pulses (-20.0) are increased always by a factor 10 after an effective stress time of 100 has elapsed. For example, beginning with a high level time of = and a constant low level time of = = (duty cycle 10), the first stress run is performed for 1,000, corresponding to an effective stress time of 100. The second stress run is performed with = and = (duty cycle 50) for 200, corresponding again to an effective stress time of 100 and to a total effective stress time of 200. The following stress runs (each lasting for an effective stress time of 100) are then performed serially on the same device with increasing until a total effective stress time of 1,000 is reached (last high level time = ). At the end of each stress run, a CP measurement was performed for 1 and subsequently a drain current measurement at -1.1 in order to monitor the stress and recovery induced evolution of interface state creation and shift.

The experiment was performed on three different devices using different recovery intervals () of 0.0 (DC), 100 and 1. The degradation of the CP current and the increase of the threshold voltage shift are illustrated in Fig. 3.9 (a), and (b) respectively, as a function of the high level stress time () (upper x-axis) and as a function of the effective stress time (lower x-axis) for the three different recovery intervals ().

From Fig. 3.9 (a) it becomes obvious that a stress interruption phase of only 100 is already sufficient to suppress degradation considerably. A huge gap (indicated by the double arrows) arises between the DC and the AC stress experiments which becomes narrower with increasing stress intervals in comparison to the constant recovery intervals (increasing duty cycle). A second remarkable detail of Fig. 3.9 (a) regards the CP recovery measured for 1 after each complete stress run (visualized by three measurement points). Indeed, recovery is not observed before the stress interval exceeds the recovery interval by at least a factor 100 indicating a correlation between the degradation and the recovery rate. For instance, the device, subjected to AC stress with a low phase of 100, begins to recovery not before the high level interval exceeds 10. On the other hand, the device, subjected to AC stress with a low phase of 1, begins to recover not before the high level interval exceeds 100. Note that the total amount of recovery obtained for DC stress (full symbols) is always the same independently of the effective stress time and the degradation level. Again very good qualitative agreement is obtained between the CP results depicted in Fig. 3.9 (a) and the shifts illustrated in Fig. 3.9 (b).

Based on the AC stress experiments discussed in this chapter we conclude that degradation is most efficient under DC bias conditions. The longer the stress bias is applied without interruption, the larger is the amount of degradation at the end of stress. Consequently, it is not the effective stress time that governs degradation but the time interval where the stress bias is continuously applied. Interrupting the stress phase by only 100 turned out to be already sufficient to influence the degradation dynamics considerably. Furthermore, a correlation between the time interval of uninterrupted stress and CP current recovery was found. When applying AC stress, CP current recovery does not proceed before the high level time exceeds the low level time by at least a factor of 100. Good qualitative agreement between the CP current increase and the threshold voltage shift was demonstrated for various AC stress conditions indicating that interface state creation plays a crucial role for the NBTI effect.