7.2 Interaction of hydrogen with degradation and recovery dynamics

In the previous section it has been demonstrated that the recovery rate is independent of the hydrogen budget within the gate oxide. This is a strong indication that the oxygen vacancy is the responsible precursor for . The following subsections study the time evolution and the energetic distribution of recoverable and quasi-permanent damage. Experiments are performed on selected hydrogen split wafers.

7.2.1 Energetic distribution and dynamic evolution of recoverable oxide traps

In this subsection, the energetic distribution and dynamics of the recoverable component is investigated in detail for three selected split wafers with different power-metalization and hydrogen budget within the gate oxide [186]. The applied technique is the ‘incremental sweep technique’ demonstrated in Subsection 6.3.3 [174].

During BEOL processing, titanium layers of different thicknesses were incorporated below the metalization in order to control the hydrogen diffusion from the upper hydrogen rich SNIT layer toward the gate oxide during fabrication. Titanium is known to be an effective barrier against hydrogen diffusion [187]. Hence, it is assumed that wafers with thick titanium barriers have less hydrogen within the gate oxide than wafers with thin titanium barriers. In this study three selected split wafers which provide vastly (about an order of magnitude) different hydrogen concentrations within the gate oxide are analyzed. This is demonstrated in Fig. 7.4 by the considerably different virgin CP characteristics.

Wafer (SM6P/30/H1) and wafer (SM6P/30/H2) are supposed to have a well passivated interface (thin Ti liner much hydrogen low CP signal) while wafer (SM6P/30/H3) has a weakly passivated interface (thick Ti liner few hydrogen high CP signal). In the following, different PMOS devices of the selected split wafers were stressed for 10/100/1,000/10,000 at 125 °C.

After each stress run, degradation was quenched to -60 °C and the devices were analyzed using the ‘incremental sweep’ technique, cf. Subsection 6.3.3. The outcome includes (i) the time dependent recovery rates within the first 100 () after the termination of stress, (ii) the recoverable oxide trap profiles extracted from the incremental sweep (), (iii) the quasi-permanent shifts () and (iv) the CP currents measured at the end of each characterization run (). The results are illustrated for increasing stress times in Fig. 7.5.

The effective density of state profiles of all split wafers are illustrated in Fig. 7.5 (a). All samples show very similar recoverable DOS profiles indicating that the trap precursor is actually independent of hydrogen, consistent with the results gained from the alternative wafer split discussed in Section 7.1. The measured recovery rates during the first 100 constant gate bias phase are illustrated in Fig. 7.5 (b). In agreement with the DOS profiles, all samples show similar recovery rates of which slightly increase with stress time. On closer inspection of the energetic profile () two characteristic peaks emerge; the first one is located near midgap and is almost fully developed after ten seconds of stress; the second one is located in the upper half of the silicon bandgap and develops gradually with further increasing stress times. The quasi-permanent shifts (; measured for 100 directly after the sweep procedure at -1.5) and the increase in the CP current (; measured directly after by gate pulsing) are illustrated in Fig. 7.5 (c1) and (c2) as a function of the stress time. and correlate by a multiplicative factor consistent with previous results. The quasi-permanent damage is considerably larger for wafer (well passivated interface) than for wafer (weakly passivated interface) indicating that both components are directly linked to each other and to hydrogen. An exception is found in wafer (equipped with a different power-metalization PM 2) which has a similar ‘zero hour’ CP signal as wafer (cf. Fig. 7.4) and hence a comparably passivated interface but shows considerably less quasi-permanent damage. Except for the metalization, wafer was identically fabricated as wafer . The quasi-permanent damage follows a power-law-like increase for all tested structures, the value of the exponent, however, increases proportionally to the hydrogen budget within the gate oxide.

In this subsection the density of state profiles of recoverable oxide traps was analyzed by making use of the ‘incremental sweep’ technique. In particular, two peaks located energetically in the middle and in the upper half of the silicon bandgap were investigated. By comparing three PMOS devices taken from selected split wafers, recovery was found to be independent of the hydrogen budget and the metalization process while the increase in the CP current and the quasi-permanent shift is strongly connected to the BEOL fabrication.

7.2.2 Interaction of hydrogen with recoverable and quasi-permanent damage

Two selected hydrogen split wafers (wafer (SM6P/30/H1) and wafer (SM6P/30/H3)) were subjected to a particularly designed experimental procedure in order to separate time and bias dependent recoverable damage from apparently quasi-permanent degradation, which is assumed to consist of interface states and locked-in oxide charges, cf. Fig. 6.27. Wafer has a thin Ti barrier and hence a lot of hydrogen within the gate oxide while wafer has a thick Ti barrier and hence a worse passivated interface. This is demonstrated by the considerably different initial CP currents and the different hydrogen signals detected with TOFSIMS, cf. Fig. 7.6 (a), and (b), respectively. Both wafers were fabricated with a standard power-metalization (PM 1).

The TOFSIMS image in Fig. 7.6 (b) shows the sub-metal BEOL layer stack of the two selected split wafers. Displayed are the oxygen and the titanium signals for the orientation within the BEOL stack. Underneath the Ti liners considerably different hydrogen concentrations are measured for wafer and in the post metal dielectric (PMD), the gate-poly and the gate oxide (GOX). In perfect agreement with the TOFSIMS results we obtain in Fig. 7.6 (a) that the initial CP signal of wafer (0.3) is about 30 times lower than the ‘zero hour’ CP signal of wafer (9.0). This is consistent with the assumption that the interface of wafer ( = 2.310 eV cm) is more efficiently passivated with hydrogen than the interface of wafer ( = 6.910 eV cm). The CP currents were recorded at a temperature of 50 °C using a pulsing frequency of 500 and rising/falling slopes of 10, scanning roughly 500 of the silicon bandgap around midgap.

The characterization procedure following NBTS (200 °C; 7.0) for a defined stress time () is illustrated in Fig. 7.7 (a). By making use of the in-situ polyheater technique, the recovery phase can be performed at a much lower characterization temperature of 50 °C which decelerates thermodynamical recovery mechanisms and improves the charge pumping measurement resolution (degradation quenching).

After stress, the characterization procedure is initiated by a 1,000 lasting recovery phase at -2.0 (t). The relative amount of recovery during t between the first measured point after removal of the stress bias (40 post stress) and the last measured point (1,000 post stress) is denoted as the time dependent recovery contribution (). Subsequently to t, the gate bias is ramped down in 20 steps from strong inversion (-2.0) toward depletion (0.0) (S). In parallel, the shift is monitored as a function of the gate bias. One full gate bias ramp takes approximately 10. Approaching depletion, the Fermi level moves from the valance band edge toward the conduction band edge, thereby gradually changing the ratio of free holes and electrons at the interface. After staying for 10 at 0.0 (t), the gate bias is ramped back to -2.0 (S). The difference in the shift recorded at -2.0 at the beginning of S and at the end of S is denoted as the bias-dependent recovery contribution (). After the first ramp down-up cycle, the maximum CP current is recorded for 10 by pulsing the gate junction between strong inversion (-2.0) and accumulation (+1.0) at a frequency of 500 (t). In the analysis, the maximum CP signal is converted into an interface state dependent threshold voltage shift () by assuming an amphoteric nature of interface traps [89] and a flat density of state profile [37], cf. Subsection 2.2.2. After the CP cycle, a short 10 lasting constant gate bias phase at -2.0 (t) is performed followed by a second down-up ramp (S; t; S). This basic MSM procedure is repeated six times on both devices of the wafer split with increasing stress times (1/10/100/1,000/10,000/100,000).

The shifts measured during the different stages of the experiment are illustrated for wafer (thin Ti/high H) in Fig. 7.7 (b) and for wafer (thick Ti/low H) in Fig. 7.7 (c). Shown are six curves corresponding to the six subsequent stress runs. In Fig. 7.8, the individual shifts are depicted separately for both wafers as a function of the stress time.

The following characteristics are obtained: (i) within the initial 1,000 constant bias phase in strong inversion (-2.0), a similar amount of time dependent recovery () is obtained for both H-levels, cf. Fig. 7.8 (a1); (ii) the total shift decreases during S and increases during S, cf. Fig. 7.7 (b) and (c); (iii) a significant bias dependent reduction in the shift is observed after S which is again similar for both H-levels, cf. Fig. 7.8 (a2); (iv) after the intermediate CP cycle, the remaining degradation level is quasi-permanent and cannot be reduced further by an additional gate bias ramp toward 0.0, cf. Fig. 7.7 (b) and (c); (v) The remaining quasi-permanent shift () and the interface state dependent shift () are much larger for wafer than for wafer , cf. Fig. 7.8 (b1) and (b2); (vi) the interface state dependent shift is smaller than the quasi-permanent shift but scales with when multiplying by a factor 3; (vii) The power-law exponents ( and ) are larger for wafer than for wafer causing faster degradation of the well passivated sample.

These seven findings on the bias and time dependence of the recovery, on interface state creation and on quasi-permanent damage, as a function of the H budget within the gate oxide, represent a comprehensive collection of NBTI characteristics. In the following, the single statements are cross-checked against our microscopic model presented in Fig. 6.27.

• (i) Recovery over time is independent of the H-level: This agrees with our model which predicts the recoverable path (path A) to be nearly independent of the hydrogen budget within the gate oxide except for the small fraction of recoverable damage being converted to locked-in oxide charge by hydrogen capture from the interface (path B), cf. Fig. 7.8 (a1).

• (ii) The shift depends on the read-out gate bias: This agrees with our model which suggests that oxide traps and/or interface states may be neutralized and become positively charged again as the Fermi level crosses the silicon bandgap, cf. Subsection 6.3.1.

• (iii) Ramping the gate bias toward 0.0 accelerates recovery, the effect being independent of the H-level: Agrees with our model which suggests bias dependent neutralization and relaxation of positively charged hydrogen-independent oxide defects.

• (iv) The degradation level is quasi-permanent after the first down-up double ramp and the intermediate CP cycle: Our model explains this by the bias-accelerated relaxation of recoverable oxide defects. A large portion of oxide defects is assumed to be removed after the first double ramp, making the remaining shift appear as quasi-permanent within the scope of our experiment.

• (v) The remaining quasi-permanent shift is much larger for the H-rich wafer: Agrees with our model considering that the larger quasi-permanent damage of the H-rich wafer is a logical consequence of its initially higher Si–H precursor concentration at the interface.

• (vi) is smaller but proportional to : Provided that the conversion of the CP signal into an interface state dependent shift is correct, this statement agrees with our model which suggests to be the sum of locked-in oxide defects and a comparable amount of charged interface states ( = + ). Due to the simultaneous creation of and via hydrogen exchange between passivated interface states and centers, the model suggests a physical 50:50 relation and a strong correlation between and . The deviation in the measured factor 3 from the proposed factor 2 (50:50) may be due to different energy distributions of interface and oxide charges, leading to a different electrical responses of both trap types.

• (vii) The power-law exponent of quasi-permanent damage depends on the passivation degree of the interface: Consistent with our model considering that a well passivated interface (wafer ) provides a larger amount of weak Si–H bonds which get broken more readily upon electrical stress.