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6.2 On the temperature dependence of NBTI recovery

As demonstrated in the previous section, poly resistors around the device can be used to perform fast and reliable in-situ heating on a single device on wafer level. The following sections address the question how such a feature can be used to perform NBTI stress at a certain stress temperature, which generates a certain degradation level, while the recovery itself can be studied at arbitrary recovery temperatures. By turning the heater on during stress and switch it off during recovery, the tool enables us on the one hand (i) to bring identically processed devices to the same degradation level and on the other hand (ii) to fix a different temperature or vary the temperature in a defined way during recovery. By using this technique, our understanding of the recovery physics can be probed in a novel manner.

The motivation for temperature switches is, for example, to clarify whether the observed recovery dynamics, demonstrated in Chapter 3 are thermally activated or not. From a physical point of view, thermodynamic models are often linked to mobile hydrogen which can diffuse toward the gate oxide during recovery thereby passivating or creating dangling bonds at the SiO (math image) /Si interface and inside the bulk of SiO [165, 166, 96, 147, 94]. However, by contrast previous experiments dealing with bias switches during recovery, cf. Chapter 5 and [145, 78, 167], demonstrated that hydrogen reaction and diffusion cannot be made responsible alone for degradation and recovery. As a solution carrier trapping via elastic tunneling was suggested [167]. However, an elastic tunneling process would be definitely too fast to explain long term recovery over many decades in time for ultra thin gate oxide devices. From a theoretical point of view such fundamentally different physical phenomena should show completely different dependencies on experimental parameters like the gate bias, the temperature and the recovery time. Also, the often observed log-like time dependence of (math image) recovery over many decades of time or the bias and temperature dependent acceleration of degradation (cf. Section 3.4) requires a consistent physical explanation. To put in a nutshell, until now the microscopic degradation and recovery mechanisms as well as the relative amount and correlation of different contributions to the total threshold voltage shift and recovery are still controversial points in literature which require an unambiguous clarification in order to probe and formulate reliable degradation and recovery models [168, 169].

6.2.1 The principle of degradation quenching

A trivial problem encountered in the observation of temperature effects in NBTI recovery is the need to dispose of a set of (i) comparable devices that are brought to (ii) the same degradation level by identical stress, but which then (iii) recover at different temperatures.

The first condition (comparable devices) may be solved by careful sample selection, involving thorough characterization before stress. Statistics indicate that a good correlation between the degradation levels observed in equally fabricated devices on the same wafer is to classify them by their virgin CP current. The zero hour CP current gives information about the initial interface state density of the device and about the concentration of hydrogen stored in the oxide. The second condition (identical degradation level before recovery), however, cannot be solved by classically available stress and characterization methods, if the third condition (various recovery temperatures) has to be maintained. Classical methods are either based on performing stress and recovery at the same temperature, or strictly separate stress and recovery by a long, scarcely observable and basically undefined transition period. While the first approach can provide the observation of recovery at very good time resolution [170], it obviously always violates condition (ii) if condition (iii) is fulfilled and vice versa.

Therefore, in order to conserve the degradation level during cooling, the temperature switch has to be fast, well controlled and independent of the difference between stress temperature and recovery temperature. This demand cannot be fulfilled by a conventional thermo chuck system since the cooling duration of such systems is very long (>30 $\,\mathrm {min}$ ) and strongly depends on the target temperature. As a consequence, one has to deal either with additional degradation when maintaining the stress bias applied during cooling or with uncontrolled recovery when leaving the device floating during cooling. Furthermore, applying a bias during the temperature switch is difficult (if not impossible) due to contact difficulties related to thermal expansion of probe needles and metal pads. In short, using the thermo chuck for temperature switches suffers from a lot of unacceptable systematic errors and drawbacks.

Figure 6.6: (a) The principle of degradation quenching. Subsequently to the initial characterization phase at the analyzing temperature $T_\mathrm {R}$ and the gate bias $V_\mathrm {TH}$ , the heater is turned on, elevating the device temperature quickly toward the stress temperature $T_\mathrm {S}$ . Once at $T_\mathrm {S}$ , the stress phase is initiated by switching the gate bias from $V_\mathrm {TH}$ to $V_\mathrm {GS}$ . After the stress time $t_\mathrm {S}$ has elapsed, the heater is turned off. The stress bias remains applied for a delay time $t_\mathrm {D}$ until the device is at $T_\mathrm {R}$ (degradation quenching). The recovery cycle ( $t_\mathrm {R}$ ) is then initiated by switching the gate bias from $V_\mathrm {GS}$ to $V_\mathrm {TH}$ . (b) Threshold voltage shift as a func- tion of the delay time $t_\mathrm {D}$ . Different PMOS devices (SM6P/30/H3) were stressed for 1,000 $\,\mathrm {s}$ at $T_\mathrm {S}$ = 125 °C and $E_\mathrm {OX}$ = 6.0 $\,\mathrm {MV/cm}$ . After degradation quenching, the $V_\mathrm {TH}$ shift was monitored at $T_\mathrm {R}$ = -60 °C and $V_\mathrm {TH}$ using different delay times $t_\mathrm {D}$ .

$ T_\mathrm {R} $ — Figure 6.6: (a) The principle of degradation quenching. Subsequently to the initial characterization phase at the analyzing temperature $T_\mathrm {R}$ and the gate bias $V_\mathrm {TH}$ , the heater is turned on, elevating the device temperature quickly toward the stress temperature $T_\mathrm {S}$ . Once at $T_\mathrm {S}$ , the stress phase is initiated by switching the gate bias from $V_\mathrm {TH}$ to $V_\mathrm {GS}$ . After the stress time $t_\mathrm {S}$ has elapsed, the heater is turned off. The stress bias remains applied for a delay time $t_\mathrm {D}$ until the device is at $T_\mathrm {R}$ (degradation quenching). The recovery cycle ( $t_\mathrm {R}$ ) is then initiated by switching the gate bias from $V_\mathrm {GS}$ to $V_\mathrm {TH}$ . (b) Threshold voltage shift as a func- tion of the delay time $t_\mathrm {D}$ . Different PMOS devices (SM6P/30/H3) were stressed for 1,000 $\,\mathrm {s}$ at $T_\mathrm {S}$ = 125 °C and $E_\mathrm {OX}$ = 6.0 $\,\mathrm {MV/cm}$ . After degradation quenching, the $V_\mathrm {TH}$ shift was monitored at $T_\mathrm {R}$ = -60 °C and $V_\mathrm {TH}$ using different delay times $t_\mathrm {D}$ .

Our approach to harmonize all conditions and to get rid of the above described technical difficulties is to use the polyheater technique, cf. Fig. 6.6 (a). During stress a certain stress bias ( (math image) ) is applied to the gate and the (previously calibrated) heater generates an elevated device temperature () for a defined stress time . Before initiating the recovery cycle, the heater is switched off, the device reaching ambient (chuck) temperature within a couple of seconds (). In order to prevent any relaxation during the temperature switch, the stress bias remains applied within the delay time (math image) . During stress continues in an undefined way, but this additional degradation is assumed to be very small compared to the degradation occurring within the main stress period typically performed at a much higher stress temperature ( $T_\mathrm {S} \gg T_\mathrm {R}$ ). This was verified in Fig. 6.6 (b) where we have stressed different PMOS devices (SM6P/30/H3) for 1,000 $\,\mathrm {s}$ at $T_\mathrm {S}$ = 125 °C and $E_\mathrm {OX}$ = 6.0 $\,\mathrm {MV/cm}$ and afterwards let them recover at $T_\mathrm {R}$ = -60 °C and $V_\mathrm {TH}$ . The cooling delay time $t_\mathrm {D}$ between turning off the heater and switching the gate bias from $V_\mathrm {GS}$ to $V_\mathrm {TH}$ was varied between 0 $\,\mathrm {s}$ and 1,000 $\,\mathrm {s}$ . When using a delay time between 0 $\,\mathrm {s}$ and 1 $\,\mathrm {s}$ , the device has not reached the target temperature $T_\mathrm {R}$ at the moment the stress bias is removed, cf. Fig. 6.5. Consequently, due to the larger temperature the measured $V_\mathrm {TH}$ shift is afflicted with an error affecting predominantly the first couple of seconds after removal of the stress bias. However, when using a delay time $\geq 3\,\mathrm {s}$ , we obtain similar recovery characteristics for arbitrary delay times suggesting (i) that 3 $\,\mathrm {s}$ is sufficiently enough to reach the target temperature and (ii) that we can safely neglect additional degradation or recovery during (math image) provided the stress temperature exceeds the recovery temperature by far. Since the cooling time of the polyheater-device system is nearly independent of the temperature difference ( $T_\mathrm {S}$ - $T_\mathrm {R}$ ), statement (i) and (ii) hold independent of the recovery temperature provided $T_\mathrm {R}$ is lower than $T_\mathrm {S}$ .

Having demonstrated the ability of the polyheater technique of conserving the degradation level during the temperature switch, the actual initialization of the recovery cycle (‘time zero’) may be defined in the following as the point in time when switching the gate bias from the stress level to the threshold voltage of the device. The entire procedure is called ‘degradation quenching’. By ‘quenching’ the degradation level to an arbitrary recovery temperature in the way described above, we are going to thoroughly investigate the role of temperature in NBTI recovery in the following sections.

6.2.2 Recovery of identically stressed devices recorded at different temperatures

In order to investigate the temperature dependence of NBTI recovery, the following experimental procedure was performed on different PMOS devices (SM6P/30/STD1) by making use of the previously described degradation quenching method. During stress, the heater generates a defined interface temperature and a certain stress bias is applied to the gate, subjecting the devices to an oxide field of approximately $E_\mathrm {OX}$ = $5.5\,\mathrm {MV/cm}$ . Source and drain are at zero volts. The stress phase was performed identically for all samples, creating a unique degradation level of each device at the end of (math image) .

After 1,000 $\,\mathrm {s}$ of NBTS, the heating current is taken away and the device cools down rapidly toward the individual ambient temperature which is defined by the temperature of the underlying thermo chuck. For example, when planning to study recovery at -40 °C, the chuck has to be at that temperature already before stress. Note that the required power supply for the polyheater necessary to reach the unique stress temperature of 125 °C, is the greater the lower the base temperature of the thermo chuck. One second after the heater has been turned off, the gate bias is switched to the threshold voltage ( $V_\mathrm {GR}$ = - $1.1\,\mathrm {V}$ ) of the device which terminates the stress abruptly and initiates the recovery cycle ( (math image) ). In parallel, the drain bias is set to its read-out value ( $V_\mathrm {DR}$ = - $2.5\,\mathrm {V}$ ) in order to measure the recovery of the saturation drain current. The transition from stress to read-out bias conditions requires approximately 200 $\,\mathrm {\mu s}$ and is limited by the speed of the voltage source unit. The first measured current at the individual recovery temperature and bias conditions can be recorded about 300 $\,\mathrm {\mu s}$ after removal of the stress voltage and about one second after the heater was turned off. The time dependent evolution of the saturation drain current is converted into a stress/recovery induced threshold voltage shift [27], cf. Chapter 2.

Figure 6.7: (a) Recovery of the threshold voltage shift recorded at different temperatures after stressing all samples at $E_\mathrm {OX}$ = $5.5\,\mathrm {MV/cm}$ and $T_\mathrm {S}$ = 125 °C. Recovery condi- tions: $V_\mathrm {GR}$ = - $1.1\,\mathrm {V}$ ; $V_\mathrm {DR}$ = - $2.5\,\mathrm {V}$ ; $T_\mathrm {R}$ = -40/0/40/80/125 °C. (b) Temperature dependent recovery rate between 1 $\,\mathrm {ms}$ and 100 $\,\mathrm {ms}$ (diamonds) and between 10 $\,\mathrm {s}$ and 1,000 $\,\mathrm {s}$ (triangles).

$ E_\mathrm {OX} $ — Figure 6.7: (a) Recovery of the threshold voltage shift recorded at different temperatures after stressing all samples at $E_\mathrm {OX}$ = $5.5\,\mathrm {MV/cm}$ and $T_\mathrm {S}$ = 125 °C. Recovery condi- tions: $V_\mathrm {GR}$ = - $1.1\,\mathrm {V}$ ; $V_\mathrm {DR}$ = - $2.5\,\mathrm {V}$ ; $T_\mathrm {R}$ = -40/0/40/80/125 °C. (b) Temperature dependent recovery rate between 1 $\,\mathrm {ms}$ and 100 $\,\mathrm {ms}$ (diamonds) and between 10 $\,\mathrm {s}$ and 1,000 $\,\mathrm {s}$ (triangles).

The result of such a temperature quenched recovery measurement is illustrated in Fig. 6.7 (a). The unique stress temperature, supplied by the polyheater, was 125 °C. The individual recovery temperatures were -40/0/40/80/125 °C. Stress and recovery durations were 1,000 $\,\mathrm {s}$ respectively. As can be seen in Fig. 6.7 (a), the recovery curves look quite similar except for a temperature dependent offset which is already present at the first measurement point recorded 300 $\,\mathrm {\mu s}$ after removal of the stress field. Although the recovery temperature was varied by more than 160 K with respect to the individual analyzing temperatures, there is no significant long-term temperature dependence visible in the recovery slopes. The recovery traces are apparently parallel.

In Fig. 6.7 (b) the recovery rate per decade is evaluated more precisely for the first one hundred milliseconds and for the last two decades of the recovery traces. On closer inspection, there is a temperature dependence visible within the first 100 $\,\mathrm {ms}$ right after stress. We observe an increasing slope of the recovery curves with increasing temperatures. While at -40 °C the amount of recovery is only 1 $\,\mathrm {mV}$ per decade, it is about three times larger for temperatures above 80 °C. A reason for the initial temperature dependence might be the fact that the device is probably not exactly at the target temperature after the short cooling delay time ( (math image) ) of only 1 $\,\mathrm {s}$ , cf. Fig. 6.6 (b). A few seconds after the termination of stress all traces become nearly parallel independent of . After 10 $\,\mathrm {s}$ the decrease of the threshold voltage shift has leveled off to about 2 $\,\mathrm {mV/dec}$ for all samples. This holds at least for two or three decades in time.

The offset can be explained qualitatively by assuming an inelastic tunneling process and a homogeneous distribution of trap energy levels responsible for the observed log-like recovery traces. When lowering the analyzing temperature, all recovery time constants increase simultaneously, thereby shifting the entire recovery characteristics to larger recovery times. After demonstrating further examples, the issue is going to be discussed in detail by means of a first order model in Subsection 6.3.4. It has to be mentioned that a possibly remaining small offset can be explained by the temperature dependent position of the Fermi level at the threshold voltage. While at low temperatures the Fermi level is closer to the valence band edge, it moves further toward midgap the higher the analyzing temperature. Considering creation of interface states within the silicon bandgap as a result of NBTS, their charge state (occupation probability) is governed by the position of the Fermi level, cf. Fig. 2.2. Consequently, at lower temperatures more of them tend to be positively charged which is reflected by a larger threshold voltage shift. The temperature dependent variation of the Fermi level apparently causes a systematic error which is, however, believed to be too little to explain the full offset.

In summary, the obtained recovery characteristics are quite surprising, in particular, when considering that degradation during stress has usually a significant temperature dependence, cf. Section 3.4. A crucial point here is that the temperature independence of the recovery rate challenges models based on hydrogen dominated relaxation. For instance, in dispersive diffusion models hydrogen is believed to be stored in traps within the oxide, at the interface or somewhere else close to the interface. In order to passivate stress induced damage, the H atoms or H $_\mathrm {2}$ molecules have to be released from there and overcome a thermodynamic barrier. At lower temperatures the probability of release as well as the diffusion rate of hydrogen is much lower. Considering such a mechanism to be the controlling process, one would expect freezing of recovery at -40 °C. However, time dependent recovery is still observed even at such relatively low temperatures. The same argument also holds for the switching of hydrogen from a bonding to an antibonding Si–H configuration, as proposed by [171]. Since the transfer from a bonding to an antibonding configuration is a thermodynamical process, it should be highly temperature activated.

Figure 6.8: (a) Virgin CP current characteristics recorded at the individual recovery temperatures. The lower the temperature, the higher the CP signal due to a larger profiled active energy range ( $\Delta E_\mathrm {CP}$ ). (b) The remaining CP current degradation at the end of the constant bias recovery phases performed at different temperatures. CP setup: $V_\mathrm {GB}$ = $1.0\,\mathrm {V}$ ; $V_\mathrm {GH}$ = - $2.0\,\mathrm {V}$ ; $f$ = 500 $\,\mathrm {kHz}$ ; $t_\mathrm {r}$ = $t_\mathrm {f}$ = 375 $\,\mathrm {ns}$ . The remaining CP signal is the larger the lower the temperature, how- ever, when accounting for the temperature dependent active energy interval ( $\Delta E_\mathrm {CP}$ ), the obtained differences in the uncorrected $\Delta I_\mathrm {CP}$ data (open symbols) is removed. The corrected data (full symbols) reveals a similar remaining degradation level of the interface after 1,000 $\,\mathrm {s}$ constant bias recovery at different temperatures.

$ \Delta E_\mathrm {CP} $ — Figure 6.8: (a) Virgin CP current characteristics recorded at the individual recovery temperatures. The lower the temperature, the higher the CP signal due to a larger profiled active energy range ( $\Delta E_\mathrm {CP}$ ). (b) The remaining CP current degradation at the end of the constant bias recovery phases performed at different temperatures. CP setup: $V_\mathrm {GB}$ = $1.0\,\mathrm {V}$ ; $V_\mathrm {GH}$ = - $2.0\,\mathrm {V}$ ; $f$ = 500 $\,\mathrm {kHz}$ ; $t_\mathrm {r}$ = $t_\mathrm {f}$ = 375 $\,\mathrm {ns}$ . The remaining CP signal is the larger the lower the temperature, how- ever, when accounting for the temperature dependent active energy interval ( $\Delta E_\mathrm {CP}$ ), the obtained differences in the uncorrected $\Delta I_\mathrm {CP}$ data (open symbols) is removed. The corrected data (full symbols) reveals a similar remaining degradation level of the interface after 1,000 $\,\mathrm {s}$ constant bias recovery at different temperatures.

In order to investigate the role of interface states in the recovery process, CP measurements were performed at the end of the 1,000 $\,\mathrm {s}$ lasting constant bias recovery phases which are performed at different temperatures. Considering that the obtained (math image) shifts are considerably different (at the end of the recovery phases), one would expect a similar difference in the remaining CP current as well provided interface state re-passivation is the dominating recovery mechanism. Such a difference is actually obtained, the -40 °C data showing a considerably larger (math image) than for example the 125 °C data, cf. uncorrected data in Fig. 6.8 (b).

However, considering the temperature dependence of the scanned energy interval (cf. Fig. 2.8 (a)), the obtained difference turns out to be afflicted with a systematic error. The error may be corrected by referencing to the initial offset of the virgin CP currents recorded at the individual analyzing temperatures, cf. Fig. 6.8 (a). We remark that all samples show a similar virgin CP current, when recorded at the same temperature. After accounting for the temperature dependent offset, the remaining shift in the CP currents becomes independent of temperature, cf. corrected data in Fig. 6.8 (b). The result indicates that either no interface state recovery takes place at all, or interface state recovery is independent of temperature. We further note that the remaining offsets in the (math image) shifts at the end of the recovery phases () cannot be explained by different interface state densities.

Figure 6.9: (a) Recovery of the maximum CP current (continuous CP) recorded at different temperatures after stressing all samples at $E_\mathrm {OX}$ = $5.5\,\mathrm {MV/cm}$ and $T_\mathrm {S}$ = 125 °C. Bias and temper- ature conditions during recovery: $V_\mathrm {GB}$ = $2.0\,\mathrm {V}$ ; $V_\mathrm {GH}$ = - $2.0\,\mathrm {V}$ ; $f$ = 1 $\,\mathrm {MHz}$ ; $t_\mathrm {r}$ = $t_\mathrm {f}$ = 125 $\,\mathrm {ns}$ ; $T_\mathrm {R}$ = -60/10/80 °C. The CP currents measured at the individual analyzing temperatures are illustrated before stress ( $I_\mathrm {CP}^\mathrm {vir}$ - full symbols) and after stress ( $I_\mathrm {CP}^\mathrm {str}$ - open symbols). (b) The scaled recovery traces of $\Delta I_\mathrm {CP}$ after stress. Independently of the recovery temperature, all samples show a similar recovery rate leaving behind approximately 70 $\,\mathrm {\%}$ of the original degradation (measured 0.1 $\,\mathrm {s}$ post stress) after 1,000 $\,\mathrm {s}$ of pulsed recovery.

In order to investigate the temperature and time dependence of CP current recovery, a similar experiment as the one presented in Fig. 6.7 (a) was performed on a different PMOS devices (SM6P/30/STD2). After stressing all DUTs under the same stress conditions (125 °C; $E_\mathrm {OX}$ = $5.5\,\mathrm {MV/cm}$ , $t_\mathrm {S}$ = $1,000\,\mathrm {s}$ ), we have quenched degradation and monitored this time the CP current recovery immediately after the termination of stress. The recovery phase was performed under continuous gate pulsing conditions for 1,000 $\,\mathrm {s}$ at three different temperatures ranging from -60 °C to 80 °C.

As can be seen in Fig. 6.9 (a), due to the temperature dependence of the active energy interval, a systematic offset in the CP signal and different recovery rates appear. However, when scaling all curves to the first measured point (0.1 $\,\mathrm {s}$ post stress), they coincide (cf. Fig. 6.9 (b)) showing a unique recovery rate of 6.5–7.2 $\,\mathrm {\%/dec}$ . In particular, there is a decrease in all CP signals of about 30 $\,\mathrm {\%}$ within four decades in time (0.1 $\,\mathrm {s}$ – 1,000 $\,\mathrm {s}$ ). The relative decrease is the same for all recovery temperatures indicating temperature independent interface state recovery during continuous gate pulsing.

6.2.3 Identically stressed devices subjected to abrupt temperature switches

In Fig. 6.10 (a) the (math image) recovery is illustrated for four different PMOS devices (SM6P/30/STD1). All devices were stressed at an oxide field of 5.5 $\,\mathrm {MV/cm}$ and at a temperature of 125 °C for 1,000 $\,\mathrm {s}$ . Three reference devices recovered at a constant temperature of -40 °C, 40 °C, and 125 °C, respectively. The forth device was subjected to two abrupt temperature switches by making use of the polyheater technique. Right after stress it recovered for 1 $\,\mathrm {s}$ at -40 °C, then for 100 $\,\mathrm {s}$ at 40 °C and finally for another 10,000 $\,\mathrm {s}$ at 125 °C providing two decades of inspection at each particular temperature. As can be seen in Fig. 6.10 (a), when elevating the device temperature abruptly, (math image) relaxation becomes accelerated approaching gradually the 40 °C reference curve, respectively, the 125 °C reference curve after a couple of seconds. Temperature accelerated recovery at constant gate bias conditions can definitely not be ascribed to elastic tunneling.

In Fig. 6.10 (b) we have performed the complementary experiment to Fig. 6.10 (a): at first, the device recovered at 80 °C for 10 $\,\mathrm {s}$ . Afterwards, the heater power was lowered so that the device cooled down to 40 °C. However, as opposed to accelerated recovery as a consequence of heating, cooling leads to frozen recovery for a certain interval of time. Indeed, recovery does not proceed before the cooled measurement curve reaches the 40 °C reference curve. Again, frozen recovery at constant gate bias conditions cannot be ascribed by an elastic hole trapping model.

Figure 6.10: (a) Two step heating performed during constant bias recovery. Reference measurements at -40/40/125 °C are illustrated by open diamonds/triangles/crosses. Recovery can be accelerated twice as we heat the device abruptly from -40 °C to 40 °C (after 3 $\,\mathrm {s}$ ) and form 40 °C to 125 °C (after 100 $\,\mathrm {s}$ ), cf. full symbols. (b) Cooling performed during constant bias recovery. Reference measurements at 40/80 °C are illustrated by open triangles/circles. Lowering the recovery temperature (80 °C $\rightarrow$ 40 °C) leads to frozen recovery until the cooled (full symbols) reaches the reference curve at 40 °C.

6.2.4 Identically stressed devices subjected to temperature ramps

In order to investigate the temperature dependence of the CP current and the (math image) recovery in a more sophisticated way, the ‘simple’ temperature switch experiments was extended to full temperature ramps. This means, the device temperature was not changed abruptly by one or two large steps but was carefully increased in many small steps beginning at a relatively low temperature (i.e.: -60 °C) and ending up finally at a much higher temperature (i.e.: the stress temperature: 125 °C). Note that a careful heater and device calibration has to be performed in advance in order to accomplish the heater power $\rightarrow$ device temperature conversion and in order to investigate the individual threshold voltage shifts recorded at different device temperatures. All PMOS devices (SM6P/30/H1) discussed in the following were stressed at an oxide field of 5.5 $\,\mathrm {MV/cm}$ and at a temperature of 125 °C for 1,000 $\,\mathrm {s}$ .

Figure 6.11: The recovery of the threshold voltage shift within the different stages of the temperature ramp experiment. The recovery sections (A/B/C/D) are depicted separately as a function of time. Note that during the temperature ramp in section (B) the time axis is linear. In section (A) at -60 °C a standard log-like $V_\mathrm {TH}$ recovery rate of 1.06 $\,\mathrm {mV/dec}$ is observed. During the tempera- ture ramp in section (B) the $V_\mathrm {TH}$ shift is reduced considerably by 16 $\,\mathrm {mV}$ . Within section (C) at 125 °C recovery proceeds again log- like with are recovery rate of 1.17 $\,\mathrm {mV/dec}$ . As we finally cool down abruptly from 125 °C to -60 °C in section (D), the $V_\mathrm {TH}$ degradation level remains frozen for the next 1,000 $\,\mathrm {s}$ .

$ V_\mathrm {TH} $ — Figure 6.11: The recovery of the threshold voltage shift within the different stages of the temperature ramp experiment. The recovery sections (A/B/C/D) are depicted separately as a function of time. Note that during the temperature ramp in section (B) the time axis is linear. In section (A) at -60 °C a standard log-like $V_\mathrm {TH}$ recovery rate of 1.06 $\,\mathrm {mV/dec}$ is observed. During the tempera- ture ramp in section (B) the $V_\mathrm {TH}$ shift is reduced considerably by 16 $\,\mathrm {mV}$ . Within section (C) at 125 °C recovery proceeds again log- like with are recovery rate of 1.17 $\,\mathrm {mV/dec}$ . As we finally cool down abruptly from 125 °C to -60 °C in section (D), the $V_\mathrm {TH}$ degradation level remains frozen for the next 1,000 $\,\mathrm {s}$ .

After degradation quenching toward -60 °C, the temperature ramp experiment can be divided in four separate sections (A/B/C/D), cf. Fig. 6.11. The gate bias remains constant at (math image) during the entire recovery phase. Section (A) was performed immediately after the termination of stress and lasts for 100 $\,\mathrm {s}$ at a temperature of -60 °C. Section (B) is the actual temperature ramp where the device temperature was increased incrementally within 125 $\,\mathrm {s}$ from -60 °C toward 125 °C in 48 equidistant (3.85 °C) steps. Having reached 125 °C, the temperature remains fixed for another time interval of 1,000 $\,\mathrm {s}$ in section (C). Before section (D) the polyheater was switched off thereby returning abruptly back to the initial characterization temperature of -60 °C for another 1,000 $\,\mathrm {s}$ .

In section (A) a log-like recovery characteristic is observed at -60 °C. The recovery rate per decade within this section is approximately 1.0 $\,\mathrm {mV/dec}$ . After 100 $\,\mathrm {s}$ , we start a linear temperature ramp in section (B) beginning at -60 °C and ending up at 125 °C. As a consequence of heating, the observed (math image) shift is reduced considerably by 16 $\,\mathrm {mV}$ indicating temperature accelerated defect annealing. In the following section (C) performed at 125 °C, we obtain again a similar log-like recovery characteristic of the shift as in section (A). The recovery rate in section (C) is approximately 1.2 $\,\mathrm {mV/dec}$ . In the last section (D), where we finally switch the temperature abruptly from 125 °C back to -60 °C, the degradation level remains frozen for the next 1,000 $\,\mathrm {s}$ . Note that the last measured (math image) shift value of section (C) and the first measured shift value of section (D) agree perfectly, although measured at vastly different characterization temperatures. This, on the one hand, confirms the reliability of our shift extraction method for different temperatures and, on the other hand, proves that the observed temperature dependent recovery acceleration in section (B) is actually a real chemical relaxation effect and not a measurement artifact associated with different characterization temperatures.

To investigate CP current recovery under comparable experimental conditions, a similar experimental procedure was performed on a different PMOS device, cf. Fig. 6.12. To record the maximum CP current, the gate junction was pulsed between accumulation (2.0 $\,\mathrm {V}$ ) and inversion (-2.0 $\,\mathrm {V}$ ) during recovery, using a pulse frequency of 500 $\,\mathrm {kHz}$ and rising/falling times of 100 $\,\mathrm {ns}$ .

In order to estimate the systematic error in the CP signal caused by the temperature dependence of the active energy interval, an initial temperature ramp experiment was performed without subjecting the device to NBTI stress. Note that the evolution of the resulting $I_\mathrm {CP}^\mathrm {vir}$ curve reflects solely the temperature dependence of the CP current without being distorted by any recovery. As discussed in Subsection 2.2.2, by increasing the temperature, the scanned energy interval within the silicon bandgap becomes narrower because of the higher emission probability of previously captured inversion/accumulation carriers during the falling/rising edges of the gate pulses. As opposed to the unstressed device, the stressed CP signal $I_\mathrm {CP}^\mathrm {str}$ may be influenced by time and temperature dependent recovery mechanisms as well. In general, we expect that during the temperature ramp $I_\mathrm {CP}^\mathrm {str}$ will decrease (i) because of a contraction of the active energy interval ( (math image) ) and (ii) because of chemical interface state repassivation of stress induced P $_\mathrm {b}$ centers.

Figure 6.12: The virgin (gray diamonds) and the stressed (black diamonds) CP currents measured during the temperature ramp experiment. The sections (A/B/C/D) are depicted separately as a function of time. Note that during the temperature ramp in section (B) the time axis is linear. In section (A) we observe a log-like CP current recovery at -60 °C. During the temperature ramp in section (B) both $I_\mathrm {CP}^\mathrm {vir}$ and $I_\mathrm {CP}^\mathrm {str}$ decrease considerably due to the shrinking of the active energy interval at elevated temperatures. Within section (C) at 125 °C, only very small additional CP current recovery is obtained. When finally cooling down from 125 °C to -60 °C in section (D), the CP signal increases again abruptly due to the expanding of the active interval. The CP signal is frozen for the following 1,000 $\,\mathrm {s}$ at -60 °C.

In Fig. 6.12, the virgin (gray diamonds) and stressed (black diamonds) CP currents are illustrated within the different sections of the experiment as a function of time. $I_\mathrm {CP}^\mathrm {vir}$ was recorded before stress, $I_\mathrm {CP}^\mathrm {str}$ was recorded after stress. Following Fig. 6.12, we obtain a decrease in the virgin CP current during the temperature ramp in section (B) which is due to the narrower active energy interval at higher temperatures. Within the sections (A), (C) and (D), the virgin CP current $I_\mathrm {CP}^\mathrm {vir}$ is constant. After the last temperature switch from 125 °C to -60 °C (section (D)) the same $I_\mathrm {CP}^\mathrm {vir}$ is obtained as in section (A) indicating that neither recovery nor stress has occurred as long as the device was not subjected to electrical stress. The reduction of $I_\mathrm {CP}^\mathrm {vir}$ within section (B) can be attributed completely to a reduction in the active energy interval.

As opposed to the virgin CP current $I_\mathrm {CP}^\mathrm {vir}$ , the stressed CP current $I_\mathrm {CP}^\mathrm {str}$ does not exclusively decease in section (B) but also in section (A) and (C) where the temperature is constant. This suggests that moderate interface state recovery probably also occurs during the 125 $\,\mathrm {s}$ lasting temperature ramp in section (B). At the beginning of section (C) (-60 °C), the CP current increases again considerably because of the temperature switch and nearly reaches its previous value obtained at the end of section (A). This indicates that the amount of real chemical interface state relaxation during section (B) and (C) is actually small (10 $\,\mathrm {\%}$ ). Consequently, the main reason for the observed decrease of the $I_\mathrm {CP}^\mathrm {str}$ signal in section (B) must be the active energy interval which is getting narrower with increasing temperature. We remark that during section (B) $I_\mathrm {CP}^\mathrm {vir}$ and $I_\mathrm {CP}^\mathrm {str}$ agree perfectly when multiplying $I_\mathrm {CP}^\mathrm {vir}$ by a factor of 2.3. This again suggests that chemical relaxation during heating is almost negligible which is consistent with the observation that CP current recovery is apparently independent of temperature, cf. Subsection 6.2.2.

6.2.5 Conclusions – T-dependence of $\Delta V_\mathrm {TH}$ and CP current recovery

Based on the upper key experiments performed on identically stressed PMOS devices, one may draw the following conclusions on the temperature dependence of (math image) and CP current recovery:

1. Threshold voltage recovery is accelerated considerably by elevating the temperature. On the other hand, when decreasing the temperature during recovery, the degradation level remains frozen for a certain interval of time.
2. The mechanism causing recovery at elevated temperature is a true chemical relaxation process which is not reversible by subsequent device cooling.
3. CP current recovery is only marginally influenced by either heating or cooling, suggesting interface state repassivation to play only a minor role in recovery as long as the gate bias is maintained constant around the .
4. The recovery rates of the shift and the CP current (recorded under continuous gate pulsing conditions) are widely independent of temperature. This holds at least for long-term recovery measurements recorded between 1 $\,\mathrm {s}$ and 1,000 $\,\mathrm {s}$ after the termination of stress.

Since our measurements show both bias (cf. Chapter 5) and temperature dependence (cf. Chapter 6), but support neither elastic tunneling nor interface state repassivation, a different mechanism has to be responsible for the observed recovery characteristics. Because bias dependence is totally incompatible with a diffusion process of neutral hydrogen species, we take the observed read-out voltage sensitivity as an indication for a trapping/detrapping phenomenon and attempt to expand the idea of elastic carrier exchange to a temperature sensitive model.

As opposed to elastic tunneling, inelastic phonon assisted tunneling is temperature dependent [172]. Oxide defects and valence band electrons having different energetic positions cannot exchange carriers elastically. However, if they gain energy from lattice vibration (phonons) they may pass the thermodynamical tunneling barrier (math image) with a certain temperature dependent probability [173].

The lifetime of a single trap can be expressed by an Arrhenius law:

$(6.1) \{begin}{align} \label {e:tau-eb} \tau (\Delta E_\mathrm {B}, T_\mathrm {R}) = \tau _\mathrm {0} \exp {\left (\frac {\Delta E_\mathrm {B}}{k_\mathrm {B} T_\mathrm {R}}\right )}, \{end}{align}$

where $\tau (\Delta E_\mathrm {B}, T_\mathrm {R})$ is the inelastic tunneling lifetime of a single trap, $\tau _\mathrm {0}$ is the pseudo-elastic tunneling exchange time between a trap and a substrate carrier at a barrier height zero, (math image) is the thermodynamical tunneling barrier, is the Boltzmann constant and is the analyzing temperature. At a constant temperature the time constants of different traps are solely determined by their individual barrier heights .

When assuming NBTI recovery to be mainly determined by the neutralization of positive oxide defects via electron capture from the silicon substrate (respectively hole emission into the silicon substrate), the observed threshold voltage recovery can be interpreted as a continuous decay of traps with different barrier heights (math image) .

Figure 6.13: First order model of temperature dependent recovery effects using a simple picture of three different traps having three different time constants, barrier heights, respectively. Each trap is assigned to an arbitrary threshold voltage shift of 1x $\,\mathrm {mV}$ . Heating or cooling shifts the recovery curve to the left or the right (shorter or longer time constants) resulting in stimulated or frozen recovery. The diamond indicates a hypothetic temperature switching event.

$ \,\mathrm {mV} $ — Figure 6.13: First order model of temperature dependent recovery effects using a simple picture of three different traps having three different time constants, barrier heights, respectively. Each trap is assigned to an arbitrary threshold voltage shift of 1x $\,\mathrm {mV}$ . Heating or cooling shifts the recovery curve to the left or the right (shorter or longer time constants) resulting in stimulated or frozen recovery. The diamond indicates a hypothetic temperature switching event.

Based on this idea, we can schematically illustrate the (math image) recovery curve for three different traps having different thermodynamical barrier heights, cf. Fig. 6.13: According to their individual barrier heights, each trap has a certain characteristic time constant at which it recovers with maximum probability. A variation of temperature ( $T_\mathrm {R1} \longrightarrow T_\mathrm {R2}$ ) impacts all time constants in parallel thereby shifting the plateaus along the time axis in log scale.

The respective shift in time for a trap with barrier height (math image) can be calculated as

$(6.2) \{begin}{align} \label {e:log-tau-eb} \log \left (\tau (\Delta E_\mathrm {B}, T_\mathrm {R1})\right ) - \log \left (\tau (\Delta E_\mathrm {B}, T_\mathrm {R2})\right ) = \frac {\Delta E_\mathrm {B}}{k_\mathrm {B} T_\mathrm {R1}} - \frac {\Delta E_\mathrm {B}}{k_\mathrm {B} T_\mathrm {R2}}. \{end}{align}$

For $T_\mathrm {R2} > T_\mathrm {R1}$ , the plateaus will shift to the left since the time constants of all traps will decrease, for $T_\mathrm {R2} < T_\mathrm {R1}$ the time constants increase leading to a shift to the right. Note that the widths of the plateaus are proportional to (math image) . The trap level which recovers first ( $\tau _\mathrm {1}$ ), has the lowest barrier ( $\Delta E_\mathrm {B1}$ ) and is therefore least temperature dependent. On the other hand, trap levels with higher barriers ( $\Delta E_\mathrm {B2}$ and $\Delta E_\mathrm {B3}$ ) depend stronger on temperature which results in a more significant temperature impact on the plateau broadness.

In this first order model, heating or cooling the device during recovery leads to stimulated recovery (at the diamond, stepping from the solid to the dashed line in Fig. 6.13, cf. Fig. 6.10 (a)) or frozen recovery (at the diamond, stepping from the solid to the dotted line in Fig. 6.13, cf. Fig. 6.10 (b)) compatible with our measurement results. When further assuming that the barrier (math image) itself can be lowered by a bias change, the model covers also bias change experiments and includes ‘mathematically’ elastic tunneling in the limit $\Delta E_\mathrm {B}$ = 0. Furthermore, homogeneously distributed thermodynamical barriers would lead to a large variety of time constants resulting in a large number of small steps like the ones described in Fig. 6.13. In a realistic experiment (large device), one would therefore expect large amounts of small steps to be smeared out as a straight line in a $\log (t)$ diagram consistent with our recovery experiments.