Having a precise degradation/recovery model in mind, this chapter aims to identify the link between hydrogen incorporation into the gate oxide and the formation of quasi-permanent and recoverable damage. Hydrogen incorporation is controlled by different modifications in the back-end process which improve the performance and defect densities of virgin silicon devices [180]. This can be done either directly by exposing the wafers to pure hydrogen or forming gas anneals [181, 182] or indirectly as a consequence of plasma-enhanced chemical vapor deposition (PECVD) of silicon nitride (SNIT) layers [183]. Such layers are considered to be efficient hydrogen sources since they contain a large concentration of hydrogen [184, 185] which may be released during or after deposition to diffuse toward the gate oxide. Provided there is no diffusion barrier below the SNIT, some hydrogen may reach the gate oxide where it can passivate dangling bonds at the interface, thereby improving the ‘zero hour’ performance of the MOS device. However, once passivated, previously captured hydrogen may be released from the interface during NBTS, leaving behind donor-like P centers that are reported to cause a negative shift in the threshold voltage of a PMOS transistor. Thus, one may expect that the initial passivation degree of the interface, namely the total number of Si–H bonds present at the interface before stress, crucially determines the NBTI sensitivity of the technology. This is a generally accepted fact often reported in literature. However, concerning the underlying micro-structural physics behind degradation and recovery, different models come to different conclusions and hence make different predictions. In order to check fundamental statements of our model with respect to the impact of hydrogen, wafer splits were fabricated, where the hydrogen budget within the gate oxide (and hence the number of Si–H bonds at the interface) was modified. Hydrogen incorporation is measured analytically by time of flight secondary ion mass spectrometry (TOFSIMS) analysis (counting secondary H ions) and electrically by CP measurements (counting dangling bonds at the interface).
The first wafer split which is going to be investigated consists of three selected wafers which differ in the back-end processing with respect to the layer and annealing sequences and the distance between the SNIT layer and the gate oxide. A schematic drawing of the individual layer stacks is given in Fig. 7.1. During the BEOL fabrication of wafer (SM5P/30/H1) the SNIT layer was deposited directly on metal 1. Wafer (SM5P/30/H2) was fabricated similarly as wafer except for the fact that the sequence of power-metalization and SNIT layer was transposed (SNIT above power metal) and an inter-level dielectric was deposited between metal 1 and the power-metalization. Also, the annealing sequences of Wafer and Wafer were different. The fabrication of wafer (SM5P/30/H3) was stopped after metal 1 deposition.
Considering that SNIT deposition introduces a lot of hydrogen into the device stack, Wafer is supposed to have the best passivated interface because the distance between the hydrogen source (SNIT) and the gate oxide is smallest. During annealing, hydrogen is assumed to diffuse from the SNIT layer toward the gate oxide. Wafer has its SNIT layer above the power-metalization and above an additional inter-level dielectric. Hence, the distance toward the gate oxide is much larger, and consequently, the interface of wafer is supposed to be less well passivated than the interface of wafer . The processing of wafer was aborted after metal 1 and no SNIT layer was deposited. Hence, wafer is supposed to have the worst passivated interface after fabrication.
The speculation concerning the hydrogen incorporation into the gate oxide and the passivation degree of the interface was confirmed electrically by means of CP measurements (cf. Fig. 7.2 (a)) and analytically by means of TOFSIMS measurements (cf. Fig. 7.2 (b)).
In agreement with the TOFSIMS results, wafer provides the lowest initial CP signal, wafer has an intermediate CP current and wafer has the highest CP signal before stress. Note that the hydrogen signal in Fig. 7.2 (b) is peaked at the interface. According to the generally accepted assumption that P centers at the interface become passivated by hydrogen, a well saturated gate oxide is supposed to degrade more rapidly under NBTI stress since it provides initially more Si–H precursors at the interface [180]. Following Fig. 7.2 (a), this hypothesis is confirmed by the variable increase of the CP current measured after subjecting PMOS devices of the particular split wafers for 1,000 to NBTI stress (125 °C; 5.2). Within the stated stress time wafer degrades most heavily, wafer shows a medium shift and wafer degrades least. Another remarkable aspect of Fig. 7.2 (a) is the fact that wafer provides the largest CP signal at the end of stress thereby exceeding wafer and wafer . Actually, the CP current order is inverted after 1,000 NBTI stress suggesting that the hydrogen incorporated during the back-end process does not only passivate dangling bonds at the interface but optionally also creates new Si–H precursors making the total amount of Si–H precursors plus P centers larger for a well passivated gate oxide, i.e. wafer .
In order to further check statements of the Grasser model with respect to the impact of hydrogen, a certain recovery experiment was performed on all three process split wafers, cf. Fig. 7.3 (a).
Right after stress, the recovery was monitored for 10 at -1.1 in order to determine the recovery slope (). Note that all wafers show a similar recovery rate of about 1.2–1.4, although the overall degradation level is significantly different. This is consistent with our model (cf. Fig. 6.27), which predicts the recoverable component ( centers) to be independent of hydrogen while the quasi-permanent contribution depends considerably on hydrogen. In order to extract the quasi-permanent component from the total shift, two bias switches were performed, one toward depletion (-0.3) and the other toward accumulation (+1.0). At the end of the last recovery cycle the remaining shift is assumed to be permanent within the time scale of our experiment. Obviously, the remaining quasi-permanent damage is largest for the well passivated wafer and least for the metal 1 wafer . A subsequent CP measurement shows perfect agreement between the quasi-permanent shift () and the increase in the CP signal () consistent with the model and with previous observations. A remarkable detail of Fig. 7.3 (a) is the ‘reverse recovery’ observed in the shifts after the gate bias switches. A certain amount of ‘reverse recovery’ is obtained for each device, however, it is most significant for wafer . This is consistent with our model when assuming ‘reverse recovery’ caused by charging and discharging of locked-in oxide defects. Considering that such locked-in oxide traps are created as a result of hydrogen exchange between passivated P centers and electrically active centers, wafer is expected to show enhanced ‘reverse recovery’ since it is assumed to provide more locked-in oxide traps (with larger time constants) after NBTI stress.
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