2 Electrostatics of NBTI degradation

This chapter addresses origins of NBTI induced drain current degradation in the linear and in the saturation operation regime of the transistor. The gate bias dependence of the threshold voltage shift is discussed theoretically and by means of a case study without taking time dependent degradation and recovery dynamics into account. An electrostatic treatment of the problem is basically justified when the time delay between stress and measurement is large enough so that defect relaxation during the measurement may be neglected.

Having identified the main causes of device degradation under DC bias conditions, the second part of this chapter introduces an experimental approach based on high frequency AC gate pulsing, allowing to separate charged defect classes which normally remain indistinguishable in a conventional DC experiment. This is because in DC experiments any kind of charged defect affects the threshold voltage shift in a similar way independent of its microscopic nature. Due to this superposition, it is not straight-forward to assign a certain contribution of the shift to a particular defect.

2.1 Effects of NBTI on analogue transfer characteristics

When stressing a MOS device under NBTS, we generally observe a variation in the drain current () when measuring the same operating point (under the same bias conditions) again after stress. The linear and the saturation drain current of a long-channel PMOS transistor (such as mostly considered here) above the threshold voltage of the device can be approximated by the following equations [19]:

where the saturation drain voltage () is approximately given by

and the physically defined threshold voltage can be derived as

In Eq. 2.1 and Eq. 2.2, the two unstable device parameters that may cause a degradation in the drain current during NBTS are the effective inversion carrier mobility () and the threshold voltage () of the device. The relative variation of the drain current as a function of the overdrive can be obtained by calculating the total derivative of Eq. 2.1 and Eq. 2.2:

Eq. 2.5 and Eq. 2.6 demonstrate that the total degradation of the drain current is directly proportional to the change of the effective carrier mobility and to the change of the threshold voltage shift divided by the gate bias overdrive (). In the saturation region, the threshold voltage degradation has a larger influence on the drain current degradation than in the linear region making the signal vs. noise resolution as a function of the shift about two times better when measuring in the saturation region of the device. From Eq. 2.5 and Eq. 2.6 we further conclude that the measurement resolution of the drain current degradation is expected to decrease linearly, when increasing the gate voltage overdrive .

Upon the build up of microscopic defects during NBTS, mobility and threshold voltage have been reported to degrade simultaneously which makes it difficult to differentiate between both effects. Once created, charged traps can act on the one hand as defect charges counterbalancing the applied gate potential () and on the other hand as Coulomb scattering centers decreasing the effective carrier mobility () and hence the on-resistance () of the device. In general, charged defects are particularly effective scattering centers when they are located close to or directly at the SiO/Si interface. Following [20, 21, 22], the effective carrier mobility () can be empirically approximated as

In Eq. 2.7 is the temperature and doping dependent low field mobility and is the number of interface states per square centimeter. The first term of the denominator in Eq. 2.7 accounts for a reduction of this low field mobility as a consequence of enhanced Coulomb scattering at surface near charge centers () while the second term considers mobility degradation caused by enhanced surface scattering when applying a vertical electric field. The coefficients and are empirical fit parameters which have to be determined experimentally from the stress induced shift in the transconductance () and from the curvature of the virgin transfer curve (). From a physical point of view, following [22] and [23], the parameter is a scattering coefficient (capture cross section) that accounts for the interaction between charged interface states and inversion layer carriers. It has the unit and may take values between (depletion) and (inversion), the lower limit being smaller due to carrier screening in deep inversion [24, 25, 26]. The parameter is the vertical field mobility coefficient [19] leading to a bending of the transfer curve in the triode region of the device. It has the unit and considers the reduction of the mobility as a consequence of the growing electric field perpendicular to the moving direction of the inversion charge carriers.

Differentiating Eq. 2.7 with respect to the interface state density () yields

Inserting Eq. 2.9 into Eq. 2.5 and Eq. 2.6, we may replace the variation in the effective mobility () by empirical constants:

Usually, when analyzing NBTI, the degradation of the drain current () is converted into a corresponding total threshold voltage shift () by assigning the drain current measured post stress a corresponding gate voltage of the virgin transfer curve [27]. Following Fig. 2.1, the difference between the actually applied gate voltage during the drain current measurement and the hypothetical gate voltage corresponding to the same drain current recorded before stress on the virgin device gives the effective shift () describing a horizontal (voltage) shift of the transfer curve that is usually a function of the current gate bias due to the curvature of the transfer curve () and due to mobility degradation caused by defect scattering (). Although the notation is somehow related to the physically defined device threshold voltage (cf. Eq. 2.4), it is also common for shifts measured at arbitrary gate voltages.

2.1.1 Influence of mobility degradation and defect charges on the total shift

As mobility and threshold voltage degrade upon the creation of various defects at the SiO/Si interface and within the gate oxide during stress, the total shift calculated from is affected by both components simultaneously, however, their relative contribution may change as a function of the gate voltage overdrive.

Defect charges modify the surface potential directly, thereby shifting the transfer curve with respect to the gate voltage axis (x-axis) (). As a consequence, the drain current is degraded () when measuring the same operating point again after stress. On the other hand, mobility degradation reduces the drain current directly due to a change in the channel resistance thereby shifting the transfer curve with respect to the drain current axis (y-axis). When converting the parasitic current reduction () caused by the degradation of the channel resistance into an equivalent threshold voltage shift, it induces an extra component () superimposed to the ‘real’ shift caused by defect charges (). The issue is discussed schematically in Fig. 2.1 where the influence of both components is illustrated separately and combined in the deep inversion regime of the transistor ().

The drain current values were calculated directly form Eq. 2.1 (neglecting for simplicity the curvature of the transfer curve () and the inversion carrier screening effect) and are plotted as a function of the gate bias overdrive. In Fig. 2.1 (a) – (c), the virgin drain current (labeled ; full diamonds) is depicted as a reference. The individually degraded drain currents are illustrated by open symbols. Fig. 2.1 (a) shows the defect charge induced shift component () as a function of the gate voltage overdrive. According to the considerably simplified drain current model described by Eq. 2.1, the stress induced shift of the transfer curve (in the triode region of the device) caused by defect charges is parallel making the reduction of the drain current () independent of the gate voltage overdrive. Fig. 2.1 (b) illustrates the parasitic shift of the transfer curve () caused by a hypothetical 30 reduction of the channel mobility. Since mobility degradation generally implies a change in the channel transconductance (slope of the transfer curve), the reduction of the drain current and hence the spurious shift () caused by surface state scattering increases linearily with the overdrive. A combination of both effects is illustrated in Fig. 2.1 (c), demostrating that the total shift () gained from the conversion of the total drain current degradation () is generally a combination of a parallel shift due to the build up of defect charges and a vertical shift due to a change in the transconductance caused by enhanced scattering at charged defect centers:

The development of the total shift with the gate voltage overdrive can be estimated from Eq. 2.10 and Eq. 2.11 by considering the curvature of the transfer curve () and the scattering at charged defect centers located at the interface:

2.1.2 Spurious shift due to mobility degradation ()

The first terms in Eq. 2.13 and Eq. 2.14 account for the spurious shifts in the linear and the saturation region of the device caused by mobility degradation. In general, the interface scattering parameter is not constant but depends on the gate bias overdrive due to the carrier screening effect [24, 25, 26]. As the density of inversion carriers increases when raising the gate voltage, they may crowd around charged point defects, thereby screening their Coulomb potential and reducing their scattering cross section. Experimental and theoretical investigations by [25, 26] revealed that the parameter decreases proportionally to the square root of the density of inversion layer carriers:

Considering the inversion carrier screening effect, the spurious shift in the linear and in the inversion regime of the device may be approximated as follows:

The result demonstrates that the mobility induced shift of the threshold voltage () is proportional to the square root of the gate bias overdrive, the curvature of the transfer curve () and the increase of the interface defect density (). As already pointed out previously, the relative contribution is found to be increasingly smaller (more than a factor 2) when measuring in the saturation region of the device.

In order to estimate experimentally, we may express the interface scattering term in Eq. 2.16 and Eq. 2.17 by the shift of the transconductance recorded after electrical stress.

The transconductances in the linear and in the saturation regime representing the slopes of the transfer curve can be calculated by differentiating Eq. 2.1 and Eq. 2.2 by the applied gate potential. The derivations are performed in the appendix (9.1):

The first terms in Eq. 2.18 and Eq. 2.19 represent the reduction of the transconductance due to field dependent scattering while the second terms consider inversion carrier screening. In particular, ons finds that the relative variations of the transconductances in the linear and in the saturation regime are directly related to the interface scattering factors in Eq. 2.16 and Eq. 2.17. The derivations are performed in the appendix (9.2). In the linear regime, we may express the interface scattering factor by the relative change in the maximum transconductance:

In the saturation regime, the deviation cannot be achieved in a straight-forward manner since the saturation transconductance has no maximum and therefore provides no characteristic operating point to refer on. In the vicinity of the threshold voltage, the variation of the transconductance may be approximated as follows:

For gate voltages far away from the threshold voltage of the device, the equations proposed above are not valid anymore and may over- or underestimate the slope of the mobility induced threshold voltage shift. This is because the development of the transconductance is expected to change considerably due to field dependent scattering and inversion layer screening. By substituting the interface scattering factors in Eq. 2.16 and Eq. 2.17 by the transconductance related expressions derived in Eq. 2.20 and Eq. 2.21, we may express the spurious shifts in the linear in in the saturation regime by experimentally measurable quantities.

In the linear regime, the mobility induced shift yields

In the saturation regime, the shift may be approximated as

demonstrating that grows proportional to the relative change of the transconductance which is originated in enhanced Coulomb scattering at stress induced interface charges. As a consequence of inversion carrier screening and field dependent scattering, the mobility induced shift does not actually increase linearly with the gate voltage overdrive as suggested in the simplest approximation illustrated in Fig. 2.1.

2.1.3  shift due to defect charges ()

Once a defect is created during NBTS, it may exchange carriers with the silicon substrate thereby being charged either positively or negatively depending on the particular energy level of the defect and on the carrier situation at the SiO/Si interface. Statistical thermodynamics stipulates that at absolute zero the quantum energy of the highest occupied quantum state in a system of fermions is defined by the Fermi energy. At finite temperatures the concept of the Fermi energy is replaced by the Fermi level (electro-chemical potential) since the separation between occupied and unoccupied states is not infinitely sharp anymore but has a half-width of approximately . In the operating temperature range of silicon devices this broadening is small (0.08 at 200 °C) so that we may generally consider defects above the Fermi level as unoccupied while traps below the Fermi level are considered as occupied.

The net charge state of a defect level generally depends on the number of electrons trapped. In principle, every defect can be amphoteric which means that it has a donor- and an acceptor-level, the first describing the defect in the positive charge state, where it may become neutralized upon the capture of one electron, the latter describing the defect in the neutral charge state, where it may become negatively charged upon the capture of an additional electron. Capture of an electron is naturally accompanied by a level shift because a higher energetic state is required. The amount of level shift depends on the local bonding environment of the defect within the solid and decides whether a defect state actually appears only in one or in in both (donor and acceptor) configurations during a particular experiment. Due to localized inhomogeneities in the lattice stress involving slight variations in the individual bonding strengths, defects close to the interface usually do not have a single energy level but a distribution of states described by a density of states (DOS) profile. The boundary between the highest donor-like state and the lowest acceptor-like state in a network of defects of the same type is called the amphoteric transition level (). In thermal equilibrium, the total defect charge may be approximated as

where is the Fermi level dependent energy range of charged defects in thermal equilibrium:

The integral in Eq. 2.24 is positive (resulting in a net positive defect charge) when the Fermi level is below , whereas the net defect charge is negative when the Fermi level lies above . It has to be mentioned that a certain time is required to restore thermal equilibrium between all kinds of defect species and the silicon substrate. The trap level only gives the equilibrium occupancy but does not say anything about the time constant. In particular, deep traps located in the bulk of the oxide having energy levels far away from the silicon bandgap, provide large carrier exchange time constants and small capture cross sections so that it may take a long time for them to align with the Fermi level. In particular, when taking inelastic carrier trapping/detrapping into account, some defects located energetically above the Fermi level may also have a finite chance to exchange carriers with the silicon substrate leading to a large variety of time constants. The dynamics of trap creation and annealing will be discussed in detail in Chapter 3.

As opposed to deep traps in the bulk of the gate oxide (slow states), defects being located energetically within the silicon bandgap and spatially close to the SiO/Si interface, exchange carriers very fast with the silicon substrate allowing to restore thermal equilibrium within a very short interval of time. Hence, the energy level of the highest occupied trap level may follow the development of the Fermi level (i.e. during a gate bias sweep) almost instantaneously. Interface states (P centers) have such attributes, in particular, they provide a wide range of energy levels within the silicon bandgap having their amphoteric transition level around midgap ( ). Following Eq. 2.24, this implies that their net charge contribution is negative when the Fermi level is located in the upper half of the silicon bandgap, zero at midgap and positive when the Fermi level lies in the lower half of the silicon bandgap, cf. Fig. 2.2. In the subthreshold region of the device, there is an almost linear relationship between the Fermi level and the gate voltage allowing defects to trap and emit carriers very efficiently. Hence, during a gate bias ramp between accumulation and inversion interface states change their net charge contribution continuously as described by the standard Shockley Read Hall (SRH) model [28]. The gate bias dependent Fermi level depicted in Fig. 2.2 was simulated numerically for a PMOS device (SM6P/30/H1) at room temperature [29].

At 0.0, when the device is turned off, the Fermi level is pinned close to the conduction band edge . Consequently, acceptor-like interface states located between midgap () and are occupied by two electrons resulting in a net negative defect charge (1). Approaching midgap (-0.5), previously negatively charged traps emit one of their two electrons resulting in an overall neutral interface at = (2). As the gate bias drives the Fermi level deeper toward inversion, donor-like defect levels located between and emit an additional electron resulting in a net positive defect charge at the threshold voltage of the device (-1.0) (3). When driving the gate bias even deeper toward inversion (-2.0), the Fermi level position does not change significantly anymore. Hence, the net positive interface charge can be considered as virtually constant once the gate bias has exceeded the threshold voltage of the device.

Except for classical interface states (SRH), it has to be mentioned that there might exist also a specific type of oxide traps ( centers, cf. Section 4.3) located close to but not directly at the interface which may have similar carrier exchanging characteristics. However, as opposed to interface states, their charging-recharging time constants are probably larger since a thermodynamic barrier has to be overcome in order to communicate electrically with the silicon substrate.

While the energetic position of an individual trap type determines its equilibrium charge state, its spatial location within the gate oxide governs its relative impact on the observed threshold voltage shift (). On a PMOS device, one usually observes a negative shift after NBTS, indicating the creation of predominantly donor-like defects which become positively charged during stress and may keep their charge state for a certain time after termination of the stress. In the case of a PMOS transistor, termination of the stress means switching the gate bias from a negative stress level to a considerably lower but also negative threshold voltage. Consequently, when recording the degraded drain current after stress, most defects remain positively charged since the Fermi level remains pinned close to the valence band edge (cf. Fig. 2.2).

Assuming a spatial distribution of positive defects , with being the distance from the gate poly interface inside the SiO gate oxide, the corresponding defect charge dependent shift () is given by Gauss’s law:

where is the area related oxide capacitance:

Note that Eq. 2.27 is only accurate for thick oxide technologies (), where the quantum-mechanical confinement of the inversion charge layer and the poly depletion may be neglected.

Assuming further all defects to be concentrated at the SiO/Si interface (), the integral in Eq. 2.26 can be easily solved, giving the following simplified expression for the defect charge induced shift:

The result demonstrates a linear correlation between the observed shift and the oxide thickness. This is an important (albeit trivial) finding, in particular, when comparing shifts of devices having different oxide thicknesses [15].

2.1.4 Relevance of defect charge induced shift and mobility degradation

Having calculated in Eq. 2.28 the real threshold voltage shift caused by electrically active defect charges () and in Eq. 2.16 and Eq. 2.17 the spurious threshold voltage shifts caused by field dependent mobility degradation (), we may estimate the relative contribution of as a function of the gate voltage overdrive by assuming all charged defects to be located at the interface:

indicating that the shift generated by defect charges is dominant when the capacitance is low (thick oxide devices), the overdrive is low and the overall interface state density is high. Considering a standard high voltage (HV) PMOS device with a 30 thick gate oxide, the curvature of the transfer curve () being -0.13, the interface density being 10, measured with an overdrive of -1.0 ( [24]), the relative contribution of to the total shift amount to approximately 92 in the linear region and 96 in the saturation region of the device which is quite large in comparison to the small remaining contribution of . In particular, in the presence of additional defect charge within the oxide which does not affect the mobility but increases the parallel shift (i.e. charge centers located in the bulk of the oxide), the contribution of may become almost negligible. However, as the oxide thickness shrinks or the overdrive increases (i.e. during on-the-fly (OTF) measurements, cf. Section 3.1) the mobility contribution can exceed up to 40 of the total shift [21] representing then an important component which has to be considered.

2.1.5 Case study

In order to demonstrate the impact of mobility degradation and defect charges on the drain current degradation and the shift, a PMOS device (SM5P/30/H1) was stressed at a temperature of 80 °C under an electric field of approximately -6.0 for several thousand seconds. Before stress, virgin transfer curves were recorded between 0.0 and -4.0 (step size 0.01) using constant drain biases of -0.05 (1), -0.10 (2) and -0.15 (3) in the linear regime () and -2.5 (4) in the saturation regime of the device (). The three transfer curves measured in the linear regime of the device are illustrated in Fig. 2.3 (a), the transfer curve recorded in the saturation regime of the device is depicted in Fig. 2.3 (b). From the measured data points (open symbols), the virgin threshold voltage and the vertical field dependent scattering factor is obtained by fitting the drain currents as a function of the gate bias overdrive according to Eq. 2.1 and Eq. 2.2. The fits are illustrated by thick solid lines yielding a threshold voltage of -0.93 and a of -0.13.

Having determined the virgin threshold voltage and the curvature parameter , we subject the device to NBTS. After stress, full transfer curves were recorded again serially in the linear and in the saturation regime of the device by ramping the gate voltage from accumulation toward inversion. It has to be mentioned that there were several seconds of delay following the termination of stress and the moment when the second set of transfer curves was finally recorded. Hence, some recovery has occurred during this floating period and during the measurement time itself. The recovery dynamics are going to be discussed in Chapter 3. In Fig. 2.4, the linear (a) and the saturation (b) drain currents recorded before (labeled ‘0’) and after NBTI stress (labeled ‘1’) at a constant drain bias of -0.1 (linear regime) and -2.5 (saturation regime) are illustrated as a function of the gate bias overdrive. The degraded transfer curves measured post stress are shifted slightly toward a more negative gate voltage indicating the build-up of positive charge.

Furthermore, the relative shift of the drain current is depicted as well in Fig. 2.4 (a) and (b) demonstrating the parameter degradation more clearly. As predicted by Eq. 2.10 and Eq. 2.11 , the relative variation of the drain current decreases gradually toward deeper inversion.

In Fig. 2.5, the transconductances in the linear (a) and in the saturation (b) regime recorded before (labeled ‘0’) and after NBTI stress (labeled ‘1’) are illustrated as a function of the gate bias overdrive. The thick solid line in (a) and (b) is a fit according to Eq. 2.18 and Eq. 2.19 which reflects the measured gradual decrease of the transconductance in the linear regime (a) and the convex curvature of the transconductance in the saturation regime (b) caused by vertical field dependent scattering (). Note that inversion layer screening has been neglected in the calculation of the fit. The relative degradation of the transconductance is also depicted in Fig. 2.5 (a) and (b), demonstrating mobility degradation and inversion carrier screening. Due to the superimposed parallel shift of the threshold voltage caused by defect charges, the relative variation of the transconductance is peaked for and decreases in the deep inversion regime due to inversion layer screening. In the linear regime (a), the relative change of the transconductance at the gate voltage at which the transconductance reaches a maximum was found to be 6.2. This is an important value since it can be used to determine the slope of the mobility induced shift, cf. Eq. 2.22. In the saturation regime (b), a larger relative change of the transconductance is measured at the same gate voltage due to the parasitic influence of , cf. Eq. 2.23. When correcting this influence, a value of 8.0 is obtained which is similar to the one extracted in the linear regime (6.2).

In the next step, the total shift is calculated as a function of the gate bias overdrive from the drain current degradation. The results are illustrated in Fig. 2.6 (a) (linear regime) and (b) (saturation regime). In Fig. 2.6 (b) we have included one result measured in the linear regime ( = -0.1) as a reference. In both regimes a similar increase of the shift is obtained below the threshold voltage of the device (I) which is assumed to be mainly caused by the gradual charging of the NBTI induced defects as the Fermi level moves from toward (cf. Eq. 2.24 and Fig. 2.2) [30, 31, 32, 33, 34, 35].

When exceeding the threshold voltage of the device, the defect charge contribution () is assumed to reach a maximum ( -0.02). This assumption is likely not completely correct since the Fermi level still moves slightly toward the valence band when increasing the overdrive, thereby charging additional defects located close to the band edge, cf. Fig. 2.2. Neglecting this second-order effect, any additional shift measured in the overdrive region (II) may be attributed to mobility degradation (). This is supported by the observation that and begin to drift apart not before entering the overdrive region (II) whereas their increase is similar in the subthreshold region (I) of the device.

As long as one only measures in the linear drain current region, the mobility dependent shift is almost independent of the drain voltage (cf. Fig. 2.6 (a)), consistent with Eq. 2.13, however, in the saturation region of the device (cf. Fig. 2.6 (b)), only about half of the increase in is observed, consistent with Eq. 2.13. The thick solid lines in Fig. 2.6 (a) and (b) are fit curves calculated analytically using Eq. 2.22 and Eq. 2.23, the offset being the defect charge dependent shift at the threshold voltage (). By inserting the curvature parameter () and the measured increase of the relative transconductance into Eq. 2.22 and Eq. 2.23, perfect agreement with the measurement data is obtained indicating that the spurious component observed in the overdrive region of the device can actually be attributed to mobility degradation caused by enhanced Coulomb scattering () at newly created charged defect centers.

From this case study we conclude that when recording the shift at an overdrive of -1, the mobility component () accounts for about 20 in the linear region and for approximately 10 in the saturation region of the device. However, when increasing the overdrive further toward -3, its contribution represents already about 35 in the linear region and about 20 in the saturation region of the device, which is then no longer negligible.