5 Bias dependence of degradation and recovery

The aim of this chapter is to study the effect of read-out gate bias and gate pulsing on the measured shift and the CP current response. In general, every variation in the gate bias corresponds to a shift of the Fermi level across the silicon bandgap, cf. Fig. 2.2. Depending on the Fermi level position, different charge densities at the interface may trigger carrier exchange mechanisms between stress-induced defects and the silicon substrate. Concerning interface states located energetically within the silicon bandgap, the carrier exchange process is assumed to happen quasi instantaneously (SRH), allowing to adjust the equilibrium charge state very quickly after a bias switch (relative to the time scales of our measurements). Following Subsection 2.1.3, this means that traps above the Fermi level are unoccupied while traps below are occupied. The net charge state changes as the Fermi level crosses the silicon bandgap during a standard gate bias ramp. As a result, we observe a variation in the subthreshold slope of the transfer curve which is usually attributed to charging of stress-induced interface states [30, 31, 32, 33, 34, 35, 142, 33]. Recent research suggests, however, that oxide traps can change their occupancy with respect to as well, which may result in an additional contribution to the variation in the subthreshold slope [35, 143, 144]. However, due to a certain spatial depth of the trapping centers within the gate oxide and due to a possible inelastic carrier tunneling process governing carrier exchange between the silicon substrate and stress-induced oxide defects, oxide trap neutralization/charging by electron/hole capture is likely to be afflicted with larger time constants as compared to SRH recombination.

Here, we extend the idea of rechargeable oxide traps with larger carrier exchange time constants than interface states and will prove that such traps have to be considered in order to explain all features of the shifts recorded at different gate biases. The position of the Fermi level at which we evaluate the threshold voltage shift will turn out to be of fundamental importance since it has a considerable impact on the extracted degradation and recovery characteristics. In a combined study, we compare threshold voltage shifts and recovery of NMOS (SM5N/30/H1) and PMOS (SM5P/30/H1) devices which allows us to gain access to the full silicon bandgap by appropriate gate biasing [145].

5.1 PMOS & NMOS Combination Technique

As we drive a device from accumulation to inversion by a gate bias sweep, we cannot reasonably measure an appropriate exponential growth in the drain current before the density of minority carriers does not exceed the density of majority carriers within the channel. In the subthreshold region of the device the Fermi level changes almost linearly with the gate voltage (cf. Fig. 2.2) and the drain current grows proportional to the majority carrier density:

Consequently, when evaluating shifts from transfer curves, the energy range between the valence band edge and the intrinsic energy () is not accessible for the NMOS device. Similarly, the energy range between and the conduction band edge () remains hidden for the PMOS device. Only by combining the study of both devices, we can maximize the accessible range of the shift evaluation versus gate voltage: on a PMOS device we have the possibility to scan roughly the lower half of the silicon bandgap by varying the Fermi level between and (hole current). By using otherwise an identically processed but oppositely doped NMOS device, which has a completely different Fermi level position for gate biases around its threshold voltage, we can scan roughly the upper half of the silicon bandgap by varying the Fermi level between and (electron current). A schematic drawing of the individual Fermi level positions is given in Fig. 5.1.

In order to generate identical stress levels by identical stress biases, we have fabricated our devices with a single gate poly process n gate material for both NMOS (SM5N/30/H1) and PMOS (SM5P/30/H1) devices. The threshold voltage of the PMOS device is approximately -1.1, while the threshold voltage of the NMOS device is roughly +1.1. We remark that despite of the different substrate and junction doping, the same stress biases applied during NBTS result in the same oxide fields and identical carrier concentrations under the gate oxide. This statement holds at least for thick oxide technologies stressed at gate biases far beyond threshold voltage (cf. Section 1.3). By studying differently doped hardware it is possible to monitor the impact of comparable degradation levels in arbitrary regions of the entire silicon bandgap. In particular, the method allows to study degradation and recovery with a majority of holes at the interface (PMOS) as well as with a majority of electrons at the interface (NMOS).

All devices discussed in the following are stressed identically for one thousand seconds at a temperature of 125 °C and a constant oxide field of 5.5. During recovery, also at 125 °C, we monitor the response of the charge pumping current and the threshold voltage shift by applying positive (NMOS device) or negative (PMOS device) gate biases around the of the individual devices. For these investigations, it is necessary to compare different sets of identically processed devices (except for the doping) with the same geometry on the same wafer (SM5P/30/H1 and SM5N/30/H1) by subjecting them to NBTI stress. In order to achieve a good correlation of the degradation levels after stress, the DUTs were selected carefully by their virgin CP characteristics. This was done because preliminary measurements have indicated a good correlation between the degradation levels observed in equally fabricated devices provided they had identical virgin CP characteristics. The zero-hour CP current gives information about the initial interface state density of the device.