5.2 Bias dependence of the CP current recovery

In Fig. 5.2 (a) the recovery of is illustrated for the NMOS and the PMOS device stressed under the same bias and temperature conditions. During CP, the gate junction of the NMOS device was continuously pulsed between -1.0 and +2.0, the gate junction of the PMOS device between -2.0 and +1.0, respectively. Except for the 1 variation in the biasing conditions (because of the different threshold voltages) both devices were measured identically using the same gate pulsing setup (rising/falling slopes 10; frequency 500). After stress, the NMOS device provides a CP signal similar to the PMOS device, indicating a similar level of interface damage. Note that within the first second of uninterrupted gate pulsing there is no significant decrease in neither for the PMOS nor for the NMOS device. This finding is in contradiction to results obtained by on-the-fly charge pumping (OFIT) measurements reported in [64] which showed fast interface state recovery immediately after terminating stress. On the other hand, within the first 100 of uninterrupted gate pulsing, the CP currents of both devices recover in a similar way by about 15, indicating time dependent re-passivation of dangling bonds at the interface [12, 140, 146, 147]. In the experiment illustrated in Fig. 5.2 (b) continuous gate pulsing was replaced by sequences of constant gate biasing (NMOS +1.1; PMOS -1.1) followed by gate pulsing. Both cycles were repeated four times with increasing cycle durations (10/100/1,000/10,000).

During the gate pulsing periods, we observe enhanced interface state recovery similar to that reported in [140, 148]. We also note that the recovery of the NMOS device is faster than the recovery of the PMOS device which may be due to the different biasing conditions during gate pulsing [149, 150]. Conversely, between two pulsing periods, where the gate bias is constant, there is rather an increase than a decrease in which indicates that previously recovered interface states may be restored again, provided the gate junction is not pulsed. The apparent ‘degradation’ of the CP current during the constant bias phases is estimated by dots in Fig. 5.2 (b). Remarkably, the increase is similar for the PMOS and NMOS devices despite of the different biasing conditions ( 1.1) indicating that the gate voltage and the carrier concentration at the interface are not crucially determining this phenomenon.

In contrast to Yang et al. [149], who concluded that the passivation of interface states is accelerated by an applied positive gate bias, and Ang [150], who suggested that the CP current recovery is suppressed by an applied positive gate bias, our experiments show unambiguously that it is the high frequency pulsing, i.e. the CP measurement itself which accelerates interface state recovery and makes it look like the ‘classic’ recovery curves illustrated in Fig. 5.2 (a). The pulsing levels and the sign of the constant gate voltage between the CP samples seems to be just of second-order importance as long as the gate voltage does not subject the device to electrical stress like in conventional OTF or OFIT measurements. The results obtained by [149] and [150] might be also misleading due to the long lasting CP measurement periods (e.g. 120 in [150]) and the large measurement delay used to determine the contributions. These observations challenge recovery theories based on interface state re-passivation [12, 140, 146, 147] and indicate that long continuous gate pulsing is not appropriate to investigate recovery during constant gate biasing.

In the following section it will be demonstrated that the interface state contribution stays quasi-permanent, consistent with [78], if we keep our CP samples shorter than one second and abstain from long continuous gate pulsing periods. This finding indicates that the observed increase of the CP current during constant gate biasing (cf. Fig. 5.2 (b)) is rather a restoration of previously recovered interface traps than a true degradation.