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Previous: 6.2 On the temperature dependence of NBTI recovery Top: 6 The role of temperature in NBTI characterization Next: 6.4 NBTI at low temperatures

6.3 Classification of defects by their recovery characteristics

Having identified the gate bias and the temperature as the main impact factors governing defect neutralization and annealing during NBTI recovery, the following investigations address a combined study of gate bias ramps and temperature switches aiming to unambiguously clarify the basic characteristics of recoverable defects introduced during NBTS. In this context, the polyheater technique allows to control temperature and gate bias independently, thereby enabling us to perform low temperature measurements right after stressing the device at a much higher stress temperature (degradation quenching). A low characterization temperature is not only beneficial since it expands the accessible energy range during CP, thereby improving the measurement resolution and the DOS approximation but also because it decelerates thermodynamical trapping/detrapping mechanisms making a larger portion of the initial degradation level visible after the termination of stress [174].

The fundamental approach of this study is to classify defects by their individual recovery characteristics. The experimental setup is particularly adapted to probe an established damage/recovery hypothesis based on $\mathrm {E}’$ centers [175, 83] that are believed to be generated as a result of NBTS and then can act as switching traps during recovery [176, 108, 152]. This so-called Harry Diamond Laboratories (HDL) model was introduced by Lelis following irradiation studies [110] later confirmed by ESR studies [102] and finally revisited and extended by Grasser et al. in the context of NBTI[144]. The microscopic model transitions involved in the classical and extended HDL model are rigorously discussed in Section 4.3.

The study clearly reveals three different types of defects. All defect types have in common that their charge state depends on the position of the Fermi level and that they introduce a broad density of state profile in the vicinity of or within the silicon bandgap. Defect (I) is fully recoverable, defect (II) is similar to defect (I) in terms of DOS but does not recover that easily, while defect (III) can be attributed to the conventional interface state (P $_\mathrm {b}$ center). From this study we come to the conclusion that the carrier trapping and detrapping characteristics of stress induced defects can be controlled by temperature and Fermi level in a similar way. However, there is also irrevocable structural relaxation which is mainly influenced by the temperature. Based on these ideas, a measurement method has been developed which can be used to energetically profile the relaxation of stress induced oxide defects.

6.3.1 Basic experimental approach and proposed underlying model transitions

To investigate bias dependent trap annealing, we study hysteresis in low temperature (-60 °C) gate bias ramps (‘down sweep’ and ‘up sweep’) after stressing PMOS devices (SM6P/30/STD2) for 1,000 $\,\mathrm {s}$ under NBTI (-5.5 $\,\mathrm {MV/cm}$ ; 125 °C). Without loss of generality, it is assumed that during stress interface and oxide traps can be created and exchange carriers with the silicon substrate. Since during stress the device is in strong inversion, the Fermi level is pinned close to the valence band edge and most interface states are considered as positively charged. Since there are almost no electrons present at the interface as long as the gate bias is at the stress level, hole capture dominates the carrier exchange process between NBTS induced traps and the silicon substrate, resulting in predominantly positively charged defects at the end of stress [140, 21, 177].

Figure 6.14: A schematic description of the trap characterization experiment. During stress at 125 °C and -5.5 $\,\mathrm {MV/cm}$ oxygen vacancy precursors (1) are believed to break up, forming positively charged $\mathrm {E}’$ centers (2). After the termination of stress, a ‘down sweep’ toward ac- cumulation is performed at -60 °C driving the Fermi level gradually from the valence band edge toward the conduction band edge, thereby neutralizing previously positively charged $\mathrm {E}’$ centers (3). Once neutralized, the $\mathrm {E}’$ center may undergo structural relaxation during the intermediate wait phase thereby restoring the original precursor state. Neutralized $\mathrm {E}’$ centers which do not undergo structural relaxation may become positively charged again during the subsequent ‘up sweep’.

$ \,\mathrm {MV/cm} $ — Figure 6.14: A schematic description of the trap characterization experiment. During stress at 125 °C and -5.5 $\,\mathrm {MV/cm}$ oxygen vacancy precursors (1) are believed to break up, forming positively charged $\mathrm {E}’$ centers (2). After the termination of stress, a ‘down sweep’ toward ac- cumulation is performed at -60 °C driving the Fermi level gradually from the valence band edge toward the conduction band edge, thereby neutralizing previously positively charged $\mathrm {E}’$ centers (3). Once neutralized, the $\mathrm {E}’$ center may undergo structural relaxation during the intermediate wait phase thereby restoring the original precursor state. Neutralized $\mathrm {E}’$ centers which do not undergo structural relaxation may become positively charged again during the subsequent ‘up sweep’.

After stress, degradation is quenched [168] from 125 °C to -60 °C. The basic experimental setup following electrical stress and the proposed microscopic model transitions linked to the gradual Fermi level sweeps are discussed in Fig. 6.14. The start of trap characterization during recovery is given by the switch of the gate voltage from the stress level (-17.0 $\,\mathrm {V}$ ) to a much lower recovery bias (-1.7 $\,\mathrm {V}$ ). As long as the new gate bias value still corresponds to strong inversion, the Fermi level remains pinned close to the valence band edge. From this point on a ‘down sweep’ toward accumulation is started turning the device gradually off. As soon as the gate bias approaches and then passes the threshold voltage ( $\approx$ -1.0 $\,\mathrm {V}$ ) during the ‘down sweep’, the Fermi level quickly moves from the valence band edge toward the conduction band edge which influences the free carrier concentrations at the interface considerably. The Fermi level positions at the particular gate voltages were simulated numerically for the tested device [29]. When approaching accumulation, new equilibrium conditions for carrier exchange between the silicon substrate and the positively charged oxide defects develop, increasingly favoring electrical neutralization of the switching traps the closer the Fermi level approaches the conduction band edge (transition (2) $\rightarrow$ (3)). Basically, this (2) $\rightarrow$ (3) transition (which we propose to call electrical neutralization, since electrically visible damage disappears upon neutralization of positively charged defects) is reversible, that is, a subsequent ‘up sweep’ leads to recapture of a hole from the substrate and restores the electrically visible damage in state (2) (transition (3) $\rightarrow$ (2)).

However, provided the defect remains electrically neutral for a sufficiently long time, the trap can undergo a structural relaxation ((3) $\rightarrow$ (1)) which lowers the defect level in energy and brings it back to the initial precursor state (1). This recovery is irrevocable (as opposed to the reversible electrical recovery mentioned before) in the sense that a re-stress is required to trigger the transition (1) $\rightarrow$ (2). Since relaxation can only occur when the trap state is neutral (that is, in state (3)), it will happen predominantly during the 10 $\,\mathrm {s}$ ‘wait phase’ of our experiment which lasts much longer than the actual ramping durations (1–2 $\,\mathrm {s}$ ). Optionally, the target bias of the ‘down sweep’ can be varied or the temperature during the ‘wait phase’ can be increased which will enhance the relaxation process (3) $\rightarrow$ (1), provided it is temperature activated. Note that increasing the temperature at a constant gate bias does not modify the Fermi level position considerably.

Our analysis is based on the observed difference in the (math image) shift between the two gate bias ramps (‘down sweep’ and ‘up sweep’)) which provides insight into the above mentioned transitions: Pure electrical neutralization ((2) $\rightarrow$ (3)) is reversible, meaning that the positive charge can be restored in the ‘up sweep’. On the other hand, a ‘real chemical’ relaxation ((3) $\rightarrow$ (1)) is irreversible under the applied bias conditions of the sweep which results in observable differences in the ‘up sweep’ compared to the ‘down sweep’.

Having explained the concept of our basic experimental approach, tailored to the physical mechanisms which we expect to observe, we will briefly summarize the detailed experimental conditions and present the results in the following subsection.

6.3.2 Individual experimental setups and results

After the stress phase, every device discussed in the following is at -60 °C and ‘per definition’ at the same degradation level. From that point on, the experiment was carried out in four different ways. The results and the individual measurement sequences are illustrated in Fig. 6.15.

Discussion on the experimental sequences

(a) Right after stress, the gate voltage is ramped down from deep inversion (-1.7 $\,\mathrm {V}$ ) toward depletion (-0.7 $\,\mathrm {V}$ ). The ‘down sweep’ takes about one second and consists of 50 equidistant voltage steps of 20 $\,\mathrm {mV}$ . After remaining for 10 $\,\mathrm {s}$ at -0.7 $\,\mathrm {V}$ , the gate junction is ramped back from -0.7 $\,\mathrm {V}$ to -1.7 $\,\mathrm {V}$ (‘up sweep’). The sequence is completed by a final charge pumping measurement.
(b) Same sequence as in (a), however, during the wait phase in depletion, the polyheater was turned on in order to heat the device to 125 °C for 10 $\,\mathrm {s}$ .
(c) Same sequence as in (a), however, ‘sweep down’ and ‘sweep up’ were recorded from deep inversion (-1.7 $\,\mathrm {V}$ ) till accumulation (+0.3 $\,\mathrm {V}$ ) the intermediate 10 $\,\mathrm {s}$ wait period being at +0.3 $\,\mathrm {V}$ .
(d) Mixture of sequence (b) and (c). During the 10 $\,\mathrm {s}$ wait period in accumulation (+0.3 $\,\mathrm {V}$ ) a heating pulse of 125 °C was applied using the polyheater.

Figure 6.15: The $V_\mathrm {TH}$ shift during ‘sweep down’ (left hand side) and ‘sweep up’ (right hand side) as a function of the read-out gate bias ( $V_\mathrm {GR}$ ). Experiments were performed accord- ing to the measurement sequences (a), (b), (c) and (d).

$ V_\mathrm {TH} $ — Figure 6.15: The $V_\mathrm {TH}$ shift during ‘sweep down’ (left hand side) and ‘sweep up’ (right hand side) as a function of the read-out gate bias ( $V_\mathrm {GR}$ ). Experiments were performed accord- ing to the measurement sequences (a), (b), (c) and (d).

In the analysis of the experiments (a) to (d) a gate voltage dependent hysteresis effect is evaluated that emerges, when the ‘down seep’ and the ‘up sweep’ are compared to the virgin transfer curve. These particular stress/recovery induced shifts are depicted as gate voltage dependent threshold voltage variations in Fig. 6.15. Note that as the gate bias exceeds depletion (-0.7 $\,\mathrm {V}$ ) and approaches accumulation (+0.3 $\,\mathrm {V}$ ) in experiment (c) and (d), the (math image) shift cannot be monitored anymore. This is a general experimental limitation originating from the lack of an inversion channel as the Fermi level approaches and finally exceeds the intrinsic level (more electrons than holes at the interface), cf. Section 5.1.

The (math image) shift in the ‘down sweep’ is identical for all experiments discussed in Fig. 6.15. A considerable reduction of by 26 $\,\mathrm {mV}$ is obtained in all setups when driving the gate voltage from deep inversion (-1.7 $\,\mathrm {V}$ ) toward depletion (-0.7 $\,\mathrm {V}$ ) right after stress. The fact that this reduction is the same for all devices serves as a consistency check considering that the measurement sequences are identical for (a), (b), (c) and (d) until the gate bias exceeds the depletion voltage of -0.7 $\,\mathrm {V}$ . The good correlation is evidence for a comparable degradation level of all devices at the end of stress. Keeping the model of energetically widely distributed oxide defects in mind, the 26 $\,\mathrm {mV}$ reduction in (math image) during ‘sweep down’ is mainly caused by electrical oxide trap neutralization as the Fermi level travels from the valence band edge toward midgap (transition (2) $\rightarrow$ (3)), cf. Fig. 6.14. Possible alternative interpretations and objections are discussed in detail by means of separate experiments in the Appendix of [174].

While ‘sweep down’ is identical for all sequences, the results of ‘sweep up’ depend significantly on the gate bias and on the temperature applied during the 10 $\,\mathrm {s}$ wait phase. According to the oxide trapping/detrapping model, the difference in the (math image) shift between ‘sweep down’ and ‘sweep up’ is mainly caused by irreversible relaxation of neutralized switching oxide traps ((3) $\rightarrow$ (1)). Repassivation of interface states and time delay effects are assumed to be negligible. Justification for these assumptions is given the Appendix of [174].

In the following, the results of the particular experimental sequences are discussed separately and agreement with the predicted structural transitions is highlighted.

Discussion of the experimental results

(a) After a 10 $\,\mathrm {s}$ wait time at -60 °C and a gate voltage of -0.7 $\,\mathrm {V}$ , the gate bias is ramped up again toward inversion (-1.7 $\,\mathrm {V}$ ). During ‘sweep up’ an increase in the shift of about 16 $\,\mathrm {mV}$ is obtained, which is, however, not as large as the amount of lost during ‘sweep down’ (26 $\,\mathrm {mV}$ ). According to the hole trapping model of Grasser et al. [144] the final difference in the shift of 10 $\,\mathrm {mV}$ between ‘sweep down’ and ‘sweep up’ can be attributed to permanently recovered oxide defects (transition (3) $\rightarrow$ (1)). On the other hand, the remaining increase of 16 $\,\mathrm {mV}$ in ‘sweep up’ indicates that electrical neutralization of oxide traps does not necessarily result in a structural relaxation which would erase them irrecoverably. Some of the defects can obviously be recharged positively again as the gate bias re-approaches inversion during ‘sweep up’ (transition (3) $\rightarrow$ (2)).
(b) This sequence studies the influence of temperature on the permanent recovery of oxide defects. As opposed to experiment (a), the device is heated up to 125 °C during the 10 $\,\mathrm {s}$ wait phase in depletion between ‘sweep down’ and ‘sweep up’. Remarkably, as a consequence of the 10 $\,\mathrm {s}$ lasting temperature pulse, a 25 $\,\mathrm {mV}$ reduction in the shift emerges, the remaining increase in ‘sweep up’ being only 7 $\,\mathrm {mV}$ . This indicates that device heating supports structural relaxation suggesting transition (3) $\rightarrow$ (1) to be temperature activated.
(c) This sequence studies the influence of a Fermi level shift toward the conduction band edge on the permanent recovery of oxide defects. As opposed to sequence (a), ‘sweep down’ in sequence (c) drives the device from inversion (-1.7 $\,\mathrm {V}$ ) till accumulation (+0.3 $\,\mathrm {V}$ ), while keeping the gate bias there during the 10 $\,\mathrm {s}$ wait phase at -60 °C. During the subsequent ‘sweep up’ again a hysteresis of about 25 $\,\mathrm {mV}$ emerges in the shift, indicating that during accumulation irrevocable oxide trap recovery (transition (3) $\rightarrow$ (1)) is much more effective than during depletion, cf. sequence (a). This is likely due to the fact that in accumulation almost all state (2) traps become electrically neutralized in state (3). Consequently, the more traps are in state (3), the higher is the possibility of a (3) $\rightarrow$ (1) transition. The remaining increase in the shift during ‘sweep up’ is considerably reduced to about 7 $\,\mathrm {mV}$ just like in sequence (b) which is consistent with the suggestion that most oxide traps visible in ‘sweep down’ have already been erased irrevocably during the wait phase in accumulation. The origin of the obtained equivalence of sequence (b) and (c) can be explained as follows: During the low temperature accumulation phase in experiment (c) most oxide traps become immediately electrically neutralized (transition (2) $\rightarrow$ (3)). Consequently, at the beginning of the 10 $\,\mathrm {s}$ accumulation phase nearly all traps are in state (3) and therefore available for the (3) $\rightarrow$ (1) transition. Although the probability of structural relaxation is low at -60 °C, some of the state (3) traps will still recover permanently within the 10 $\,\mathrm {s}$ wait phase. On the other hand, when biasing the device in depletion during the wait phase, a smaller fraction of the previously generated state (2) traps are in state (3) at the beginning of the 10 $\,\mathrm {s}$ wait phase. As a consequence, less (3) $\rightarrow$ (1) transitions are expected, cf. sequence (a). However, when heating the device in depletion (cf. sequence (b)), the temperature activated (3) $\rightarrow$ (1) transition becomes accelerated considerably. Furthermore, additional (2) $\rightarrow$ (3) $\rightarrow$ (1) transitions are likely to occur as a consequence of inelastic tunneling ((2) $\rightarrow$ (3)) and subsequent structural relaxation ((3) $\rightarrow$ (1)).
(d) A combination of sequence (b) and (c), accumulation phase plus heating pulse, leads to the highest degree of permanent relaxation. The hysteresis in the shift between ‘sweep down’ and ‘sweep up’ exceeds 30 $\,\mathrm {mV}$ which correspond to almost full recovery except for a small apparently permanent offset. It seems that nearly the entire oxide charge contribution, visible as 26 $\,\mathrm {mV}$ in ‘sweep down’, has been neutralized (transition (2) $\rightarrow$ (3)) and subsequently recovered permanently (transition (3) $\rightarrow$ (1)) by heating the device in accumulation. This is consistent with the Fermi level dependence of the (2) $\rightarrow$ (3) neutralization and the temperature acceleration of (3) $\rightarrow$ (1) relaxation. The small remaining increase of about 4 $\,\mathrm {mV}$ in ‘sweep up’ and the constant offset of 3 $\,\mathrm {mV}$ visible at -0.7 $\,\mathrm {V}$ can be attributed to interface state charging and possibly positive locked-in oxide defects emerging as a result of hydrogen exchange between passivated interface traps (Si–H bonds) and state (2) oxide traps ( $\mathrm {E}’$ centers), cf. Section 4.3.

Discussion on the role of interface states

It is an important finding that interface states (P $_\mathrm {b}$ centers) cannot be made responsible for the observed hysteresis between ‘sweep down’ and ‘sweep up’. This is demonstrated clearly by comparing the remaining (math image) shifts recorded at the end of ‘sweep up’ at -1.7 $\,\mathrm {V}$ to the remaining CP current signal recorded immediately after ‘sweep up’. The comparison is illustrated in Fig. 6.16. As a reference the shift and the CP current measured directly after the termination of stress is included and labeled ‘post stress’ at the left hand side of the figure.

Figure 6.16: Comparison of the remaining $V_\mathrm {TH}$ shifts (gray bars) to the remaining CP current signals (white bars) for the individual sequences at the end of ‘sweep up’. As a reference, the $\Delta V_\mathrm {TH}$ and the $\Delta I_\mathrm {CP}$ signals recorded immediately af- ter the termination of stress are illustrated to the left and labeled as ‘post stress’.

Following Fig. 6.16, the measured CP signal is widely independent of the individual measurement sequence and also quite the same right after the termination of stress. This is because the CP signal is mainly sensitive to interface states which are considered to be quasi-permanent. On the other hand, the remaining (math image) shift measured at -1.7 $\,\mathrm {V}$ at the end of ‘sweep up’ depend strongly on the measurement sequence. When measuring the shift right after the termination of stress (first point of ‘down sweep’ labeled ‘post stress’ in Fig. 6.16), it is found to be largest. This is because the total (math image) shift is assumed to consist of two components, the first being attributed to recoverable oxide defects ( $\mathrm {E}’$ centers), the latter being attributed to quasi-permanent locked-in oxide charges and interface states (P $_\mathrm {b}$ centers). While the recoverable contribution may be annealed with time, temperature and bias switches, the quasi-permanent contributions remain particularly the same within the scope of our measurement sequences.

Indication for additional locked-in positive oxide charges is given by the small remaining degradation level observed at -0.7 $\,\mathrm {V}$ in ‘sweep up’. Due to the fact that P $_\mathrm {b}$ centers are amphoteric [89, 90] and therefore commonly assumed to be neutral, when the Fermi level is close to midgap, the remaining (math image) shift at -0.7 $\,\mathrm {V}$ may be due to a different type of oxide defect equipped with larger time constants than conventional $\mathrm {E}’$ centers, cf. Section 4.3.

6.3.3 Energetic profiling of recoverable oxide defects

The results and conclusions drawn by the experiments described above identified the Fermi level position and the temperature as the main parameters influencing the microscopic model transitions discussed in Fig. 6.14. In order to correlate the Fermi level position to the amount of (math image) recovery, an additional extended experimental setup was developed: This ‘incremental sweep’ procedure linked to the Fermi level positions at individual gate voltages is schematically depicted in Fig. 6.17.

Figure 6.17: A schematic illustration of the ‘incremental sweep’ technique. The $V_\mathrm {TH}$ shift is measured for 100 $\,\mathrm {s}$ at a constant gate bias of -1.7 $\,\mathrm {V}$ directly post stress ( $\Delta V_\mathrm {TH}^\mathrm {pstr}$ ) and directly af- ter the incremental sweep procedure ( $\Delta V_\mathrm {TH}^\mathrm {pswe}$ ). In between, $V_\mathrm {TH}$ shift tuples are measured right before (diamonds) and right after (triangles) each double-staircase ramp ( $V_\mathrm {GH} \longrightarrow V_\mathrm {GB}^{i} \longrightarrow V_\mathrm {GH}$ ). The Fermi level positions ( $E_\mathrm {F}^{i}$ ) corresponding to the base poten- tials ( $V_\mathrm {GB}^{i}$ ) of the double-ramps are illustrated below the experimental setup. As an example, the predicted model transitions and the additionally accessible energy range ( $\Delta E_\mathrm {F}^{i,i+1}$ ) is depicted when going from an arbitrary voltage level $V_\mathrm {GB}^{i}$ to the next level $V_\mathrm {GB}^{i+1}$ .

Rather than starting with a full ‘down sweep’ immediately after stress as was done in Fig. 6.15, a 100 $\,\mathrm {s}$ lasting constant gate bias phase at -1.7 $\,\mathrm {V}$ was included prior to the actual sweeping procedure. This was done in order to differentiate between ‘time dependent’ and ‘bias dependent’ recovery effects. Within this initial 100 $\,\mathrm {s}$ , the (math image) shift was determined as a function of time ( $\Delta V_\mathrm {TH}^\mathrm {pstr}$ ). After the constant bias phase, the incremental down sweep was initiated beginning at $V_\mathrm {GH}$ = - $1.7\,\mathrm {V}$ till $V_\mathrm {GB}^\mathrm {1}$ = - $1.5\,\mathrm {V}$ followed by a constant bias wait phase of 1 $\,\mathrm {s}$ at $V_\mathrm {GB}^\mathrm {1}$ . Subsequently, the gate bias was ramped back toward $V_\mathrm {GH}$ = - $1.7\,\mathrm {V}$ which was maintained for another second. In the following, the $V_\mathrm {GH} \longrightarrow V_\mathrm {GB}^{i} \longrightarrow V_\mathrm {GH}$ double-staircase sweeps are repeated keeping (math image) constantly at -1.7 $\,\mathrm {V}$ while increasing $V_\mathrm {GB}^{i}$ incrementally by +0.2 $\,\mathrm {V}$ till a final value of +0.3 $\,\mathrm {V}$ . Right before and immediately after such a double-staircase sweep, tuples of values are recorded and referenced to the Fermi level positions corresponding to $V_\mathrm {GB}^{i}$ , cf. Fig. 6.17. After the last down-up cycle, the (math image) recovery is monitored again for 100 $\,\mathrm {s}$ at a constant gate bias of -1.7 $\,\mathrm {V}$ ( $\Delta V_\mathrm {TH}^\mathrm {pswe}$ ).

As the $V_\mathrm {GB}^{i}$ level incrementally moves from inversion (-1.7 $\,\mathrm {V}$ ) toward accumulation (+0.3 $\,\mathrm {V}$ ), the Fermi level $E_\mathrm {F}\left (V_\mathrm {GB}^{i}\right )$ increasingly approaches the conduction band edge, cf. Fig. 6.17. In fact, when going from an arbitrary voltage level $V_\mathrm {GB}^{i}$ to the next level $V_\mathrm {GB}^{i+1}$ , the accessible energy range for the (2) $\rightarrow$ (3) transition within the silicon bandgap extends by

$(6.3) \{begin}{align} \label {e:deltaE-incremental-sweep} \Delta E_\mathrm {F}^{i,i+1} = E_\mathrm {F} \left (V_\mathrm {GB}^{i+1}\right ) - E_\mathrm {F} \left (V_\mathrm {GB}^{i}\right ). \{end}{align}$

Traps within this energy range may be neutralized during the following down sweep ( $V_\mathrm {GH} \longrightarrow V_\mathrm {GB}^{i+1}$ ). Once neutralized, some of the additional state (3) traps within $\Delta E_\mathrm {F}^{i,i+1}$ may relax permanently during the 1 $\,\mathrm {s}$ wait phase at $V_\mathrm {GB}^{i+1}$ (transition (3) $\rightarrow$ (1)). The ones who made the (3) $\rightarrow$ (1) transition are finally missing in the subsequent up sweep ( $V_\mathrm {GB}^{i+1} \longrightarrow V_\mathrm {GH}$ ) and therefore account for a difference between $\Delta V_\mathrm {TH}^\mathrm {A}$ ( $E_\mathrm {F}^{i+1}$ ) and $\Delta V_\mathrm {TH}^\mathrm {B}$ ( $E_\mathrm {F}^{i+1}$ ).

Figure 6.18: The $V_\mathrm {TH}$ shifts measured during the incremental sweep experiment. The time dependent recovery of the threshold voltage shift, recorded for 100 $\,\mathrm {s}$ at $V_\mathrm {GH}$ = - $1.7\,\mathrm {V}$ directly post stress is illustrated to the left ( $\Delta V_\mathrm {TH}^\mathrm {pstr}$ ). In the mid- dle the tuples $\Delta V_\mathrm {TH}^\mathrm {A}$ and $\Delta V_\mathrm {TH}^\mathrm {B}$ corresponding to the particular base levels $V_\mathrm {GB}^{i}$ are illustrated. The difference $\Delta V_\mathrm {TH}^\mathrm {A}(V_\mathrm {GB}^{i}) - \Delta V_\mathrm {TH}^\mathrm {B}(V_\mathrm {GB}^{i})$ is representative for the number of (3) $\rightarrow$ (1) transitions happening during the $V_\mathrm {GB}^{i}$ phase. From that difference, a den- sity of state profile may be evaluated by referencing to energy gap $\Delta E_\mathrm {F}^{i,i+1}$ and to the position of the Fermi level within the silicon bandgap ( $E_\mathrm {F}^{i}$ ).

By referencing the differences $\Delta V_\mathrm {TH}^\mathrm {A}$ ( $E_\mathrm {F}^{i+1}$ ) - $\Delta V_\mathrm {TH}^\mathrm {B}$ ( $E_\mathrm {F}^{i+1}$ ) to the current Fermi level position $E_\mathrm {F}^{i+1}$ at $V_\mathrm {GB}^{i+1}$ and to the corresponding energy gap $\Delta E_\mathrm {F}^{i,i+1}$ , an average density of state (DOS) profile can be determined. The DOS profile may be calculated under the assumption that all traps are located close to the SiO (math image) /Si interface:

$(6.4) \{begin}{align} \label {e:DOX-incremental-sweep} D_\mathrm {OX}^\mathrm {rec} \left (\frac {E_\mathrm {F}^{i} + E_\mathrm {F}^{i+1}}{2}\right ) = \frac {C_\mathrm {OX}}{\mathrm {q}} \frac {\Delta V_\mathrm {TH}^\mathrm {A}(E_\mathrm {F}^{i}) - \Delta V_\mathrm {TH}^\mathrm {B}(E_\mathrm {F}^{i})}{\Delta E_\mathrm {F}^{i,i+1}}. \{end}{align}$

In Eq. 6.4, $C_\mathrm {OX}$ is the area related gate oxide capacitance, q is the elementary charge and $E_\mathrm {F}^{i}$ is the Fermi level position at the base level $V_\mathrm {GB}^{i}$ .

The (math image) shifts measured during the ‘incremental sweep’ procedure are illustrated in Fig. 6.18. The results of the 100 $\,\mathrm {s}$ time dependent threshold voltage recovery recorded right after stress ( $\Delta V_\mathrm {TH}^\mathrm {pstr}$ ) are depicted at the left hand side of Fig. 6.18. Within this time interval, a logarithmic recovery characteristic is obtained showing a slope of +2.8 $\,\mathrm {mV/dec}$ . The incremental sweep routine, which takes approximately 50 $\,\mathrm {s}$ , follows right after the initial 100 $\,\mathrm {s}$ performed at a constant gate bias of -1.7 $\,\mathrm {V}$ . The results for $\Delta V_\mathrm {TH}^\mathrm {A}$ and $\Delta V_\mathrm {TH}^\mathrm {B}$ are illustrated in the middle of Fig. 6.18 as a function of the double-sweep base potential $V_\mathrm {GB}$ . Any kind of time dependent recovery associated with the large voltage drop from stress bias (-17.0 $\,\mathrm {V}$ ) to $V_\mathrm {GH}$ (-1.7 $\,\mathrm {V}$ ) is assumed to be negligible during the sweep phase due to the 100 $\,\mathrm {s}$ time delay following the actual stress phase. What remains is mostly Fermi level and temperature controlled carrier exchange. This is consistent with the observation that the degradation level is frozen at the end of the sweep routine, cf. $\Delta V_\mathrm {TH}^\mathrm {pswe}$ in Fig. 6.18 right hand side. Note that the final degradation level of -16 $\,\mathrm {mV}$ after $V_\mathrm {GB}$ = + $0.3\,\mathrm {V}$ in Fig. 6.18 is quasi-permanent at least within the time scale of our experiment and correlates perfectly with the ‘up sweep’ in sequence (b) and (c) in Fig. 6.15.

By making use of Eq. 6.4 and Fig. 6.18, a DOS profile may be calculated for the particular stress conditions. It is illustrated in Fig. 6.19 on the left hand side.

Figure 6.19: Extracted density of state profile of permanently recovered $\mathrm {E}’$ centers which have undergone the transitions (2) $\rightarrow$ (3) $\rightarrow$ (1) during the incremental sweep procedure. The energy is referenced to the position of the Fermi level within the silicon bandgap ( $E_\mathrm {F}^{i}$ ).

From a physical point of view, this DOS corresponds to $\mathrm {E}’$ centers which are generated during stress ((1) $\rightarrow$ (2)), primarily neutralized during recovery ((2) $\rightarrow$ (3)) and finally recovered via structural relaxation ((3) $\rightarrow$ (1)). It has to be remarked that the stated energy levels $E_\mathrm {F}^{i}$ in Eq. 6.4 and Fig. 6.19 need not necessarily correspond exactly to the actual energy levels of the defects located within the oxide, especially when assuming that the carrier exchange mechanism between the silicon substrate and the state (2) trap is inelastic. The DOS profile shows a significant peak around midgap. The occurrence of this peak can in general have two different reasons:

(i) There is a large DOS of type (2) traps located around midgap. After being neutralized by Fermi level variations ((2) $\rightarrow$ (3)), many (3) $\rightarrow$ (1) transitions may occur during the 1 $\,\mathrm {s}$ wait phase at $V_\mathrm {GB}$ causing a significant reduction of positive charge at the end of the subsequent up sweep.
(ii) In general, oxide trap neutralization ((2) $\rightarrow$ (3)) and subsequent relaxation ((3) $\rightarrow$ (1)) of state (2) traps might become efficient not before the free electron concentration exceeds the free hole concentration at the oxide-substrate interface.

Based on our previous experiments, explanation (i) has to be favored: It has been shown in Fig. 6.15 that an increase in temperature during depletion has a similar impact on permanent oxide trap recovery as biasing the device in accumulation for the same amount of time, cf. sequence (b) and (c) in Fig. 6.15. Since elevating the temperature does not change the ratio of free interface carriers significantly but considerably enhances the number of (2) $\rightarrow$ (3) transitions by inelastic tunneling and simultaneously accelerates the thermally activated (3) $\rightarrow$ (1) transition, a dominance of electrons does not seem to be a mandatory requirement for relaxation.

6.3.4 Conclusions on the microscopic origin of NBTI induced defects

In this subsection switching oxide traps created during NBTS have been identified and examined. Recoverable oxide defects (most likely $\mathrm {E}’$ centers) were found to be positively charged during stress. These defects can change their charge state during recovery. According to the HDL model, one must differentiate strictly between electrical neutralization and chemical bond reconstruction. The neutralization process is influenced considerably by the temperature and by the position of the Fermi level during read-out. In the neutral charge state (3) the switching oxide trap can either undergo a structural relaxation which anneals the trap permanently ((3) $\rightarrow$ (1)) or can re-emit a previously captured carrier and become positively charged again ((3) $\rightarrow$ (2)). Although electrical neutralization was identified to be a basic requirement for chemical relaxation, the intermediate neutral trap state requires thermal activation and time in order to lower in energy and relax irrevocably. By incrementally moving the Fermi level position into the silicon bandgap, oxide trap neutralization and subsequent permanent relaxation could be stimulated in a controlled manner. By referencing the observed threshold voltage shift reduction to the position of the Fermi level, an oxide trap DOS profile could be obtained which has a significant peak around midgap. The remaining degradation, after having annealed the majority of switching traps, seems to consist of a mixture of interface states and another type of chargeable oxide trap (locked-in oxide defects).

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