So far the trapping kinetics of single defects in nanoscale devices have been described by their capture/emission time characteristics. Now this approach will be extended to large-area devices. Therefore, the capture/emission time distribution function , which gives the number of defects contributing to
within the interval
and
, is introduced. Therefrom the threshold voltage shift can be calculated via [89]
Hence defects contributing to have been charged until
and are not discharged after
. Furthermore, by reformulating (8.11) to
the capture emission time (CET) map can be directly calculated from a set of experimental recovery traces recorded for different stress times, see Figure 8.20.
Figure 8.20: (left) The recovery traces are recorded for different stress and recovery times using a high-k pMOSFET. (right) Using (8.12) the CET map is directly calculated from the measurement data. Note that the capture time refers to stress bias and the emission time refers to recovery bias. The recovery traces have been recorded with our developed measurement instrument.
Equation (8.12) is used in Chapter 12 to compare simulated CET maps with CET maps directly calculated from measurements. As will be shown, the simulations reproduce the characteristics of the experimental CET map, confirming the accuracy of this approach.
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