12 Negative Bias Temperature Instabilities in High-k SiGe Transistors

To sustain Moores' Law, conventional MOSFETs have been scaled down to the nanometer regime. However, due to the limited subthreshold slope, the device supply voltages cannot be scaled in the same manner as the device geometry without any losses of the device performance. As a consequence, the oxide fields occurring in the scaled devices increase, thereby leading to an increase of the gate leakage current. In order to avoid the detrimental increase of the gate leakage currents, high-k (HK) gate stacks together with metal gate (MG) contacts are used in state-of-the-art MOSFETs. The fabricated high-k gate stack employed in such devices typically consists of a Hafniumoxide () layer on top of a interfacial layer [2, 3, 4, 5]. Just like with transistors using or gate dielectrics, BTI is one of the most critical reliability issues in HK transistors as well.

To further enhance the performance of transistors, SiGe quantum-well pMOSFETs have been proposed [175, 176, 177, 178], see Figure 12.1 (left).

These transistors employ HK gate stacks on top of a SiGe quantum-well layer, and have been initially developed to take advantage of the higher carrier mobility of the strained SiGe layer. Quite surprisingly, it was found that NBTI is considerably smaller in these quantum-well devices. Furthermore, a strong dependence of the absolute threshold voltage shift on the Si cap layer thickness together with a stronger oxide field acceleration with respect to Si devices was reported. It has been speculated that these observations are a consequence of the energetical realignment of the SiGe channel with respect to the gate stack [175, MWC24]. As the previous observations were made on large-area devices, a more precise justification was difficult to give. As previously mentioned, using large-area devices only the average response of a large number of defects can be studied. However, to provide a more detailed understanding of this phenomenon, the impact of the individual constituents has to be studied.

To study the impact of the Si cap layer thickness on the device performance devices with two different geometries are compared, namely nanoscale SiGe pMOSFETs with a gate width of and a gate length of , and large-area SiGe pMOSFETs with . For each geometry three different device variants, namely devices with a Si cap layer thickness of and , as well as a conventional Si transistor which is the reference device, are studied. The characteristics of the corresponding devices is shown in Figure 12.1 (left). A strong correlation between the threshold voltage, extracted as the voltage at which , and the Si cap layer thickness is visible. The devices with the thin Si cap layer show the highest threshold voltage whereas the lowest values are observed for the reference devices. These different threshold voltages have to be considered during NBTI characterization when stress and recovery experiments are performed. In general, the oxide stress field can be estimated by

with the gate overdrive voltage, the effective oxide thickness, the stress voltage and the threshold voltage of the device. In order to apply similar stress and recovery oxide fields different gate voltages have to be used for the stress/measure experiments carried out at the different device variants. This is particularly important as the degradation and recovery of the threshold voltage strongly depends on the stress and recovery oxide field.

In the following section, the impact of NBTI on nanoscale and large-area SiGe HKMG pMOSFETs is investigated. Starting with the description of the device electrostatics using quantum-mechanical and classical device simulations, the device structure and doping profiles are reproduced. Next, the TDDS is used to study single defects in nanoscale pMOSFETs. By employing the four-state NMP model, see Section 7.3.3, the charge transition times of single defects are explained. Afterwards, charge trapping in large-area SiGe devices is discussed and modeled using the four-state NMP model in combination with our classical device simulator Minimos-NT. Finally, the lifetime projections which are based on our simulations are presented.

12.1 Device Simulation

At the begin of our investigations the device structure has to be created. Therefore quantum-mechanical (QM) and classical device simulations are carried out. The QM simulations are necessary to consider quantum-effects in nanoscale devices and are performed on a simplified 1D device structure. Afterwards, classical devices simulations are performed using Minimos-NT and a 2D device structure. The latter simulations are required to apply our four-state NMP model to explain charge trapping in these devices.

12.1.1 Quantum Mechanical Simulations

As the thin SiGe channel underneath the Si cap layer requires careful consideration, detailed QM simulations are carried out. These are performed by using our QM Schrödinger Poisson solver VSP to calibrate the device structures to the experimental characteristics of large-area devices with [179, 180]. This is achieved by thoroughly adjusting the individual layer thicknesses using a simplified one-dimensional structure of our transistor, see Figure 12.1. From the QM simulations the band structure and the corresponding sub-bands are obtained and shown in Figure 12.2.

The peaks of the first two wavefunctions in the subbands are located in the near the / interface. As the subbands give the probability of finding the carriers, the peaks in the suggest that the conducting channel is more likely located in the SiGe layer than in the Si cap layer. Furthermore, the charge separately calculated for the SiGe and Si cap layer at different gate biases for the different device variants is notably larger inside the SiGe layer than in the Si cap layer, see Figure 12.3.

This result confirms the previous claim that the channel is primarily in the SiGe layer and is particularly important when charge trapping is considered in these devices. The prevalent channel inside the layer will be demonstrated to be the cause for the reduced susceptibility of the device to NBTI.

12.1.2 Classical Device Simulations

Based on the layer thicknesses and bulk doping density obtained from the one-dimensional QM simulations, the two-dimensional device structures of the pMOSFETs are created. For this purpose, the classical device simulator Minimos-NT [181] is used and a quantum-corrected drift-diffusion model is solved [182].

As can be seen from Figure 12.4, the simulations which have been performed using the calibrated 2D devices nicely reproduce the experimental characteristics.

From our 2D device simulation the surface potential and the carrier concentration at the interface can be calculated. Both quantities are used in combination with the four-state NMP model to explain the intricate capture and emission times of the single defects measured on our nanoscale devices and the continuous recovery observed on large-area transistors. Note that all characteristics have been reproduced using the same devices structure with an appropriate gate area and the corresponding Si cap layer thickness.

Based on our classical device simulations the band-diagram of our SiGe devices can be calculated. In Figure 12.5 the valance and conduction band edges are shown at stress bias conditions.

In addition, the so called active energy region (AER) for charge trapping is highlighted in the band-diagram. This area is very important as it is a necessary condition for a single defect contributing to NBTI that at defined stress and recovery bias conditions the defect is energetically located inside such an AER. Only those defects which are energetically arranged inside the AER can change their charge state during stress and thus contribute to a change in the threshold voltage. The borders of the AER are defined by the considered stress and recovery gate bias. Thus at stress bias conditions the energetic level of a defect located at inside the gate stack has to lie above the corresponding Fermi level

and below the Fermi-level at recovery bias conditions

with and the position dependent potential drop across the gate stack for stress and recovery bias conditions, respectively. Furthermore, the AER region can be separated into an AER for charge trapping with the MG and into an AER for charge trapping with the conduction channel. Both AERs can be described using (12.2) and (12.3) with its corresponding Fermi levels. Additionally, the energy level of the conducting channel located in the SiGe, which is by itself determined by the dependent band offset between the Si cap and SiGe, is visible in the AER in Figure 12.5. As this certain energy level is higher than the Fermi level of the Si cap only a reduced number of defects can capture a hole from the SiGe.