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13 Permanent Component of Negative Bias Temperature Instabilities
As discussed in the previous parts of this thesis, BTI is often considered to be the sum of a recoverable and a permanent threshold voltage shift. To understand both partial contributions to this puzzling phenomenon, tremendous efforts have been put towards an explanation of the observed threshold voltage shift. In contrast to the recoverable component, the study of the permanent threshold voltage shift is even more involved s it is mostly overshadowed by the former. According to the prevalent opinion, the permanent threshold voltage shift is due to single defects with large time constants, commonly referred to as interface states [139, 185, 145, 144, 186, 156, 187]. In the following a measurement sequence deliberately designed to study the recoverable and permanent component simultaneously is introduced. By performing ultra-long time experiments over several month, the evolution of the permanent threshold voltage shift is recorded and analyzed. To explain the newly collected data the hydrogen release model, see Section 7.4.2, is used.
13.1 Experimental Characterization of the Permanent Component
To monitor threshold voltage shift due to NBTI in pMOSFETs, simple stress/measure sequences are commonly used. We extended this procedure by a set of 
sweeps, recorded prior and after the stress/measure cycle is applied, see Figure 13.1.
Figure 13.1: The measurement sequence used to determine the permanent component of NBTI is shown. (top) During stress the defects get charged, resulting in a threshold voltage shift 
. At the end of the recovery a significant remains which can be assessed by our modified measurement sequence. Using subsequent 
sweeps, a significant amount of the charge trapped during stress is removed and thus a basically flat recovery is observed at the end of the proposed measurement sequence. (bottom) As can be seen, prior and after the stress/measure cycle ten additional
sweeps are performed [MWC7].
As can be seen, the 
accumulated during stress is not completely reversed after recovery. Obviously, a significant number of defects with very large time constants is present which determine the permanent component of . To access the remaining typically ten sweeps are measured after recovery thereby removing a significant amount of the trapped charge. Next, the permanent can be extracted at different gate biases using the sweeps, see Figure 13.2.
Figure 13.2: (top) The sweeps are used to extract the permanent contribution 
to the total . (bottom) The voltage range of the sweeps allows to evaluate at different gate biases. As can be seen, during the first up-sweep is significantly larger, a consequence of the large number of trapped charges available immediately after the recovery cycle. In the subsequent sweeps only a weak change of is visible. In addition, the location of the interface states 
is shown [137]. At the corresponding gate biases a strong impact of interface states would be expected. These interface states are typically aligned 
above the valence band, but no particular shift is observed in this region [MWC7].
We define the permanent component as the difference in the gate voltage between the down-sweep 
and corresponding up-sweep 
of the measured sweeps
extracted at a certain gate bias by considering the same drain-source current. Remarkably, 
extracted from the first sweep performed from inversion to accumulation is strongly reduced towards decreasing absolute gate bias. This is a consequence of a larger number of traps remaining charged at the end of the recovery phase. In contrast, the analysis of the subsequent sweeps show a nearly flat dependence on 
. As the interface states are typically supposed to be the main culprit for , a peak arranged slightly above the 
of the pMOSFET is expected. Figure 13.2 b shows the area where contributions of interface states are expected, calculated considering
at 
above the valence band [137]. However, no contribution is this region is measured. Finally,
is taken as a measure for the permanent component remaining after our proposed measurement sequence.
In order to elucidate the evolution of , the TMI together with a computer controlled furnace is used. The latter is necessary to achieve defined device temperatures and controlled temperature gradients when the temperature is changed. Using our sophisticated setup, is studied over several month on a single transistor mounted into a conventional ceramic package. As the time constants of the defects responsible for are very large, temperature accelerated experiments are performed, see Figure 13.3.
Figure 13.3: The measurement sequence used to monitor over several month employs the temperature acceleration of charge trapping. At a reference temperature of 
20 sweeps are performed before the device is stress at higher temperature. Again, after cooling back to the reference temperature, 20 sweeps are recorded. Note that the stress bias is applied during heating and cooling phases. To obtain an accurate description by simulations these phases have to be considered [MWC6].
To minimize the measurement noise, the permanent component of is again extracted using equation (13.2).
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