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12.4 Nanoscale versus Large-Area Devices
Based on the recent experimental studies using transistors with 
or 
gate dielectrics, BTI in large-area and nanoscale devices has been attributed to defects with similar atomic configuration. Thus once the trapping kinetics of single defects is known, BTI in nanoscale and large-area and devices can be reproduced. In our particular
case, 23 single defects have been identified in the three SiGe device variants. Afterwards, the four-state NMP model is used to explain the extracted charge capture and emission times of each of the 23 single defects. From these simulations the energetical and spatial defect
position of the 23 single defects are obtained and shown in the band-diagram in Figure 12.14.
Figure 12.14: The band-diagram under stress bias conditions shows the defect bands used to explain the recovery of the large-area devices. Defects identified in the nanoscale devices are marked with larger symbols diamond
for 
, square for 
, and circle for reference pMOSFET. The single defects are located in the HK and the IL for all three studied device variants [MWJ2].
In the band-diagram the single defects necessarily have a trap level above the Si Fermi level when stress bias is applied and a trap level below the the Si Fermi level when recovery bias is applied. Otherwise the defects would not contribute to NBTI at the studied bias conditions. As can be seen, the single defects are found to be located in both the HK and the IL for all three studied device variants. As the single defects of all three technologies show a similar stress bias dependence of their capture time the distribution of the trap depth is found to be similar for all three device variants.
In addition to the single defect simulations, the defect bands used to describe the continuous recovery behavior of the large-area devices, see Figure 12.13, is also shown in the band-diagram, see Figure 12.14. A good agreement is achieved between the defect band and the defect positions of the single defects estimated by the four-state NMP model.
To study the distribution of the capture and emission times (CET), the CET maps of large-area devices can be calculated directly from the measurement data using ((8.12)) and compared to those obtained from simulations, see Figure 12.15.
Figure 12.15: The CET maps calculated directly from the measured recovery traces (top row) and the CET maps obtained from our simulations (bottom row) are compared for the three different structures (left for
, middle for 
, and right) the reference Si pMOSFET. For the simulated CET maps, the measurement window (the axis ranges of the measured CET maps), is highlighted. As expected, the characteristics of the measured CET maps is well reproduced by our
simulations. Additionally, the single defects from the nanoscale devices are shown (symbols) [MWJ2].
As can be seen, the simulations reproduce the characteristics of the measurement data very well. According to (8.12), a narrow measurement window compared to simulations is achieved for the calculated CET maps due to experimental limitations.
Furthermore, the CET datapoints from the analyzed single defects found in the nanoscale devices are marked in the CET maps together with the measurement window used for our TDDS experiments on nanoscale devices. As can be seen, the extracted single defects lie well inside the CET distribution.
Based on the previous simulations, the effective activation energies for charge capture 
and emission 
are calculated, see Figure 12.10.
Figure 12.16: The simulated thermal activation energy distribution calculated from the defects of the device with . In addition, the symbols show the activation energies of the single defects from the nanoscale transistors (diamond for , square for , and circle for reference pMOSFET). As can be seen, the single defects are spread over the same energy range as the simulated defects well, given the limits of the experiment [MWJ2].
The continuous distribution shows the activation energies of the defect band used to explain the recovery of large-area SiGe devices. In addition, the activation energies from the single defect investigations are marked by symbols. As can be seen, both the distribution and the single data points are fully consistent. This confirms that a representative ensemble of single defects has been analyzed in this work.
Finally, the lifetime projections based on the experimental data shows that the threshold voltage shift saturates towards larger stress times, which thus deviates from the typically used power law. As such, a power law approximation results in significantly underestimated device lifetimes [MWJ1]. The device lifetimes extrapolated by using the calibrated model are shown in Figure 12.17.
Figure 12.17: The lifetime estimation based on the unified model is shown against the applied gate bias. Quite remarkably, at the nominal operating voltage of 
a lifetime of more than 10 years is easily achieved for the 
devices. In particular, the devices with a thin Si cap layer have an about four orders of magnitude higher lifetime although they show the lowest threshold voltage and thus have the highest overdrive voltage [MWJ2].
As can be seen, the SiGe devices with the thinnest Si cap provide a superior lifetime, easily outperforming the Si reference device.
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