4.6 Defect Centric Perspective

Although modern devices have been dramatically scaled, gate dielectrics with a thickness around still contain thousands of atoms. Even with modern computer hardware, the computational effort involved in a direct computation of the electrical properties of the oxide using ab initio methods would be too large. As a consequence, a hierarchical simulation workflow is required for the simulation of BTI and related degradation mechanism affecting devices and circuits. The individual simulation levels are summarized in the defect centric picture [MWJ6], see Figure 4.13. The lowest level uses atomistic simulations such as DFT calculations to study the atomic structure of defects. The first abstraction level focuses on the modeling of the trapping kinetics, i.e. the capture and emission times of single traps, which can be directly measured on each single transistor. With a model explaining the trapping kinetics at hand, device transport models allow to simulate the transistor characteristics considering charge trapping. Based on these simulations, compact models can be derived which can be employed in circuit simulations. The results from the circuit simulations can be further used to study the interplay of complex components, for instance gates, flip-flops and registers, and can be extend to whole applications.