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9.2 Time-Dependent Defect Spectroscopy Measurement Instrument

In order to provide an experimental setup which allows full control of the experimental parameters, that are the output voltages and the corresponding switching behavior between different voltage levels as well as different data acquisition scheme and control output, the TMI has been invented. Although, the TMI has been initially designed to perform TDDS experiments it turned out that due to the modular design the TMI can be easily adjusted characterize large-area transistors and much more. The following section gives an overview of the design of the TMI and summarizes the main features.

9.2.1 Design of the Time-Dependent Defect Spectroscopy Measurement Instrument

The overall application of the TMI can be separated into three main tasks: (i) providing defined output voltage characteristics (static or transient), (ii) record input voltages or currents, and (iii) provide an interface between the TMI and the device under test. In addition, an external digital I/O interface for synchronization between different instruments or external devices is available. The TMI can be controlled via an USB interface.

The schematic shown in Figure 9.3 provides an overview of the modular design of the TMI.

(-tikz- diagram)

Figure 9.3:  In the standard configuration the TMI is equipped with one voltage unit (VU) providing three synchronized output voltages, two data aquisition units (DAUs) to monitor (math image) and (math image) and the device connector unit (DCU), which is the link to the device under test.

The standard configuration contains one VU providing programmable output signals, up to two DCUs used to monitor input voltage signals and providing external control lines, and one DCU as the link between the TMI and the device under test. The external control lines can be used to synchronize the DCUs with external general purpose instruments or voltage sources. Furthermore, additional hardware, such as polyheater controller units, can be connected to the TMI using the external I/O port. The voltage and data acquisition units are directly controlled via a USB interface. A backbone bus system is used to synchronize the individual units, to exchange control information and to connect the digital and shielded analog power supply.

In addition, the schematic in Figure 9.3 shows the configuration used to measure the drain-source and gate current of an nMOSFET. As can be seen, all terminals of the device under test are connected to the DCU, which provides output buffers and current to voltage converter units. The biases forwarded by the DCU are provided by the VU which is itself connected to the former. Furthermore, the single DAUs are connected to the appropriate outputs of the DCU providing measurable voltages proportional to the drain-source and gate current. Note that all outputs of the DCU are initially floating and are connected only immediately before the measurement. This is important as it has been found that even at zero gate bias MOSFETs accumulate a (math image) shift, see Chapter 13.

Voltage Unit

The concept of the VU is shown in Figure 9.4. In the entire design the digital and analog components are electrically isolated from each other in order to guarantee low noise in the analog output signals.

blockdiagramVoltageUnit.tikz

Figure 9.4:  The schematic of the VU shows the three output DACs together with the corresponding output amplifiers. The digital control lines of the processor are decoupled from the analog area. The processor itself is connected to the backbone bus system for data exchange and synchronization purposes. The bus connections between the processor and the DAC are emphasized by thicker lines.

The main unit of the digital part is an ARM processor, which also provides the USB interface for external communication. Furthermore, the processor is connected to an internal bus system to exchange control information with other modules and to provide a synchronized timing behavior. Furthermore, the digital and shielded analog power-supply are distributed by the backbone bus system.

The analog part consists of three DACs controlled by \( \SI {16}{\bit } \) data-words followed by a low pass filter stage and an additional output amplifier. The latter is necessary to drive coaxial cables and to act as short circuit protection for the preceding DAC stage. To calculate the digital data word for a given output voltage the relation

(9.1) \begin{equation} d_{\mathrm {w}} = V{_\mathrm {out}}\frac {V{_\mathrm {out,max}}}{2^{N}-1} \end{equation}

with \( N \) the number of bits provided by the DAC can be used. The data-words and the synchronization lines for each of the three DAC are decoupled from the digital area by integrated high-speed opto-couplers.

When switching between to defined voltage levels the output voltage characteristics are of particular interest. On the one hand the switching transient has to be as short as possible, while on the other hand the voltage overshoot also has to be taken into account. In general it can be said that the steeper the switching transient becomes, the larger the corresponding voltage overshoot is. To compensate for the detrimental voltage overshoot, several techniques such as pole compensation, gain compensation, lead and lead-lag compensation are used is OPAMP circuits [166]. The compensated switching transient of the developed voltage unit is shown in Figure 9.5.

(image)

Figure 9.5:  Exact switching transients when the output voltages changes are essential for reliability experiments. The rising and falling edge of the output signal of the voltage unit (VU) are measured with an oscilloscope (red symbols). As can be seen, the output amplifier is adjusted to a switching time of approximately \( \SI {200}{\nano \second } \) without any overswing.

As can be seen, the voltage unit provides a rise time and fall time of \( \trise =\tfall \sim \SI {200}{\nano \second } \) without any voltage overshoot. Following from that the maximum available output frequency is \( \fmax =\SI {1}{\mega \hertz } \).

The output current limits, output voltages ranges and the corresponding voltage resolutions are summarized in Table 9.1 and Table 9.2.

Table 9.1:  The maximum ratings for output currents defined by the corresponding output buffer.

Short Circuit Output Current \( \ImaxShortCircuit \) 90 mA
Maximum Output Current \( \Imax \) 35 mA

Table 9.2:  The two output voltage ranges which are currently available together with their corresponding voltage resolutions.

Output Voltage Range Voltage Resolutions
\( \pm \SI {5}{\volt } \) \( \VResolution =\SI {152.5}{\micro \volt } \)
\( \pm \SI {8}{\volt } \) \( \VResolution =\SI {244.1}{\micro \volt } \)
Data Acquisition Unit

The DAU has been developed to record an analog input voltage in the range of \( \Vmax =\pm \SI {2.5}{\volt } \) using a high sampling rate up to \( \fsmax =\SI {1}{\mega \hertz } \). The DAU thereby provides two operation modes with different accuracies, as summarized in Table 9.3.

Table 9.3:  The available DAU input modes and the corresponding sampling frequencies are summarized together with the measurement resolution.

DAU mode (math image) (math image)
fast mode 1 MHz 305.2 µV
normal mode 250 kHz 76.3 µV

The block-diagram of the DAU is shown in Figure 9.6.

(-tikz- diagram)

Figure 9.6:  The analog input signal is passed to the input filter with or without subtraction of a programmable offset voltage. A high precision ADC converts the analog signal to a digital-word and is controlled by a decoupled processor unit. Furthermore, the processor unit provides programmable external digital control lines. For the communication with the PC a USB interface is available.

At the analog input connector the signal can either be directly forwarded to the input filter stage or an additional voltage offset can be added followed by a subsequent amplifier. The latter pathway allows to shift the allowed input voltage range by a maximum of \( \SI {2.5}{\volt } \) in each direction. The span of the input voltage is \( \DeltaVInMax =\SI {5}{\volt } \) and the input voltage range

(9.2) \{begin}{align} -\frac {\DeltaVInMax }{2} & \leq \VIn \leq \frac {\DeltaVInMax }{2}. \{end}{align}

By adding an additional voltage offset in the range of \( \VOffset \in [\SI {-2.5}{\volt }:\SI {2.5}{\volt }] \), the provided input voltage range can be adjusted to

(9.3) \{begin}{align} \VOffset - \frac {\DeltaVInMax }{2} & \leq \VIn \leq \VOffset + \frac {\DeltaVInMax }{2}. \{end}{align}

The offset voltage \( \VOffset \) can be programmed with a resolution of \( \SI {12}{\bit } \) leading to an accuracy of \( \VResolution _\mathrm {off}=\SI {1.22}{\milli \volt } \). A subsequent amplifier and filter stage is used to suppress the DAC and amplifier noise. It has to be noted that the measurement accuracy of the ADC is independent of the alignment of the input voltage range. Especially when the focus is put on single traps, the recovery traces need to have a very high measurement resolution. The programmable input offset allows to shift the mean value of the input voltage range without any losses of the accuracy. Both switches used to select the signal path between the input connector and the filter stage are synchronized and controlled by a driver stage electrically isolated from the main processors.

The input filter and a high precision amplifier unit implemented prior to the ADC are designed to match the bandwidth of the input signal to the sampling frequency. It is of utmost importance to carefully calibrate both units in order to hold the noise level of the measured signal as low as possible and at the same time take advantage of the high sampling frequency.

As discussed in Chapter 8, for monitoring the device reliability the input signal has to be recorded for very long time ranges up to \( \SI {100}{\kilo \second } \). In order to achieve a manageable number of data-points per trace but at the same time having a high sampling time resolution, a non-uniform sampling scheme is used preferentially. In Figure 9.7 the input signal for uniformly sampled data at different sampling frequencies is shown.

(-tikz- diagram)

Figure 9.7:  Schematic traces uniformly sampled with different sampling frequencies using the current range of \( \SI {2.5}{\micro \ampere } \) which is most suitable for characterization of single charge trapping in nanoscale transistors. The variance of the uniformly sampled traces does not change during a single trace. At a smaller sampling frequency, which corresponds to a higher integration time, the variance of the signal, that is the signals noise power, decreases. To record long traces at highest speed a large data memory is necessary. Note that the buffer of the TMI available for a single trace is limited to \( 10^6 \) samples.

As expected, with a smaller sampling frequency, which is equivalent to a larger integration time, the variance of the sampled signal decreases. Thus, using a non-uniform sampling scheme the variance of the signal decreases automatically during the measurement, because the integration time is increased after each decade, see Figure 9.8.

(-tikz- diagram)

Figure 9.8:  The non-uniformly sampled data recorded with (top) 200 samples per decade (this is the most common case used in our experiments), (middle) 1000 samples per decade and (bottom) 10000 samples per decade shows a reduced signal noise power (see variances given at the bottom of each sub-figure) with increasing sampling time because the sampling frequency (given at the top of each sub-figure) is decreased. As a consequence of the adjusted sampling frequency, the measurement resolution increases automatically. Another benefit of the non-uniformly sample scheme is the reduced number of datapoints with allows to record ultra-long traces.

With the possibility of using either a uniform or a non-uniform sampling scheme, a new challenge for the subsequent data analysis algorithms arises which is discussed in Chapter 10.

Device Connector Unit

The DCU acts as the interface between the DUTs and the TMI. It provides floating output terminals which are connected to the appropriate signal lines only during the measurement. As the data aquisition unit is designed to record voltage signals, the main purpose of the DCU is to convert the currents flowing through the MOSFET terminals into voltages measurable by the corresponding DAU. To achieve a high current resolution from the milli-ampere regime down to the sub-picoampere regime and at the same time hold the noise level as low as possible, a thorough design of the analog part of the circuit layout is required.

A schematic illustration of the entire concept of the device connector unit is shown in Figure 9.9.

(-tikz- diagram)

Figure 9.9:  The output terminals of the DCU are initially floating to avoid any distortion of the devices. At the source terminal, the current convert unit (CCU) holds the source voltage at \( \VS =\SI {0}{\volt } \). By contrast, the source converter unit (SCU) allows to output a voltage and measure the current simultaneously, which is necessary for monitoring the gate current.

As can be seen, the drain and bulk terminals of the DUT are connected to the VU using intermediate amplifier stages. Furthermore, the output amplifiers provide the necessary currents and a subsequent low pass filter stage is implemented to block HF noise. At the source terminal a high-precision current convert unit (CCU) is available. The detailed configuration of the CCU is illustrated in Figure 9.10.

(-tikz- diagram)

Figure 9.10:  The CCU provides eight input current ranges selectable using synchronized switches. By using the OPAMP, the potential of the input pin is held at \( \SI {0}{\volt } \). Again, the analog and digital components are electrically isolated.

It is important to note that the potential at the input terminal is held at \( \VIn =\SI {0}{\volt } \). At the output terminal a voltage signal proportional to the input current \( \IIn \) is obtained given by

(9.4) \begin{equation} \VOut (t) = A\times \IIn (t). \end{equation}

In order to provide a wide input current range, different input gains \( A = [10^2, 10^3 \ldots 10^8, 10^9] \) can be selected. The maximum input current for the selected gain \( A \) is

(9.5) \begin{equation} I_\mathrm {max} = \frac {2.5}{A} \end{equation}

and the corresponding accuracy

(9.6) \begin{equation} \Delta I = \frac {1}{A}\cdot \frac {2.5}{2^{15}}. \end{equation}

The maximum available input voltage \( V_\mathrm {in,max}=\SI {2.5}{\volt } \) and the number of quantized values \( N_\mathrm {D}=2^{15} \) are given by the ADC providing a \( \SI {16}{\bit } \) resolution and a input voltage range of \( \pm \SI {2.5}{\volt } \). Note that for the best current accuracy provided by \( A=10^9 \) an alternative OPAMP with ultra-low input bias current has to be used and the use TRIAX components is recommended. Furthermore, the current ranges can be adjusted on demand by modifying the gain of the amplifier stage. All switches used to select the appropriate current range are synchronized and connected via the backbone bus system to the DAU. Again, the digital and analog sub-circuits are electrically decoupled.

To measure the gate current, a source converter unit (SCU) has been designed, see Figure 9.11.

(-tikz- diagram)

Figure 9.11:  The SCU operates like a general purpose SMU. A defined output voltage is provided and the current is converted to a proportional voltage at the same time. Similar to the CCU, synchronized switches allow to select the appropriate input voltage range.

In contrast to the CCU, the SCU provides a defined output voltage while the input current can be measured. For that the CCU has to be extended by an additional subtraction unit followed by a filter stage. In general, each additional amplifier stage introduces noise to the measurement signal and an additional offset voltage which has to be compensated. However, due to the final low pass unit of the SCU its noise level is similar to the noise level from the voltage signals from the CCU, see Figure 9.12.

(-tikz- diagram)

Figure 9.12:  A comparison of (top) a non-uniformly sampled signal and (top) a uniformly sampled signal measured with the CCU and SCU shows similar signal noise level. An additional low pass filter suppresses the noise level of the SCU below the noise level of the CCU although the SCU requires an additional OPAMPs.

Power Supply

In analog circuits and especially in instruments used to precisely record signals with a very high accuracy the power supply plays a crucial role. Therefore, the power supply of the TMI is thoroughly separated into a digital supply, providing the power for the processors, the USB interface and the external control lines and an analog supply which drives the very sensitive input/output terminals of the VU, the DAU, and the DCU. To emphasize the important role of a low noise analog power supply a test voltage signal is recorded, while the supply voltage of the analog part of the TMI is provided by

  • 1. the integrated power supply unit (PSU),

  • 2. a battery, and

  • 3. a switching power supply

as the main power supply of the TMI. As can be seen in Figure 9.13, the distortion caused by the switching power supply is not acceptable .

(image)

Figure 9.13:  The noise of the signal measured by the TMI is compared for power supplied by (top left) the integrated PSU (top right) a switching power supply and (bottom) a battery. As can be seen, equal signal to noise ratios (SNRs) are obtained for the signal recorded using the internal and the battery power supply. Using a switching power supply leads to a significant increase of the noise level in the signal and thus reduces the maximum achievable measurement resolution.

The best solution is to use battery powered systems or the integrated PSU which provides a reasonably low noise level.

9.2.2 Properties of the Time-Dependent Defect Spectroscopy Measurement Instrument

The figures of merit for our measurement instrument are the sampling bandwidth, which defines the smallest measurable switching transient between the stress and recovery cycle, and the minimum measurable input current, which strongly depends on the gain of the input amplifier, see Figure 9.14. While the input bandwidth is limited by the maximum sampling frequency of \( \fsmax =\SI {1}{\mega \hertz } \) due to the integrated ADC, different gains of the input signals are available providing different measurement resolutions. The minimum current resolution \( \mathrm {min}(I)\sim \SI {1}{\pico \ampere } \), which underlines the thoroughly worked out design.

(-tikz- diagram)

Figure 9.14:  (top) For small gains the signal bandwidth is limited by the maximum sampling frequency. Towards higher input gains the bandwidth is limited by the OPAMP and the input circuit. (bottom) The higher the signal gain gets, the smaller the current resolution gets. The theoretical limit is a consequence of the current resolution provided by the least significant bit of the ADC. However, the experimentally measured resolution is higher because the signal is overshadowed by measurement noise.

The correlation between the bandwidth and the minimum detectable (math image) is shown in Figure 9.15.

(image)

Figure 9.15:  For a smaller input bandwidth, that means a larger integration time, of the I/V converter stage the measurement resolution of the (math image) is significantly increased, leading to smaller measurable (math image) shifts. The minimum detectable (math image) is calculated for the two most common gains of the I/V converter which are used to study single charge trapping in nanoscale devices. This is done using the given relation between the (math image) and (math image), extracted from a measured (math image) characteristics of a nanoscale pMOSFET.

According to (7.19) the smaller the measurable current shift gets the more defects can be studied properly using the TMI. Quite remarkably, at a sampling frequency of \( \fs \approx \SI {30}{\kilo \hertz } \) the current resolution is already below \( \dVth < \SI {1}{\milli \volt } \). Furthermore, on the one hand BTI recovers very quickly and on the other hand the device recovery behavior has to be monitored for very long times, for instance \( \tRead =\SI {10}{\kilo \second } \) and even longer. Due to the limited high speed data buffer of the available instruments, linear sampling at a high frequency is not feasible. For instance, data sampled with \( \fs =\SI {1}{\mega \hertz } \) for just \( \tRead =\SI {1}{\kilo \second } \) using an ADC with \( \SI {16}{\bit } \) resolution would need a disk space of \( \SI {1.86}{\giga \byte } \). Since typically 100 traces are recorded at a number of biases and temperatures, a linear sampling scheme is not suitable to study single defects in nanoscale devices. Thus a logarithmic sampling scheme, with typically 200 samples per decade, is preferred. Note, by using the latter, the sampling frequency is increased every decade and as a consequence the current resolution implicitly is improved.

9.2.3 Output Signals

The TMI provides all output voltage signals which have been used so far in context of the TDDS, see Figure 9.16. These output modes involve

  • • DC stress signals,

  • • AC stress signals,

  • • DC stress signals with a subsequent voltage pulse and

  • • DC stress signals with a subsequent AC voltage signal.

After each stress cycle the output voltages switch to recovery bias conditions and (math image) and (math image) are monitored. In addition to the listed output signals, individual time-dependent voltage characteristics can be programmed. The listed core signals provide a time resolution of \( \SI {500}{\nano \second } \) whereas the time resolution of individuals signals is limited to \( \SI {1}{\micro \second } \).

(-tikz- diagram)

Figure 9.16:  The core output signals implemented in the TMI and the corresponding configuration are shown. The signals involve (a) DC stress signals, (b) AC stress signals, (c) DC pulse stress signals and (d) DC stress with subsequent AC stress signals.

Furthermore, custom voltage ramps can be independently configured for each output with a resolution of \( \SI {10}{\micro \second } \) in time, see Figure 9.17. From this, simple voltage sweeps as used for (math image) measurements can be derived.

(-tikz- diagram)

Figure 9.17:  Schematic of the ramp signal and its corresponding parameters: rise time \( t_\mathrm {R} \), high time \( t_\mathrm {H} \), fall time \( t_\mathrm {F} \) and low time \( t_\mathrm {L} \) as well as low voltage level \( V_\mathrm {L} \) and high voltage level \( V_\mathrm {H} \).

9.2.4 Data Acquisition

The main feature of the DAU is to record the drain-source and gate current during the stress and recovery cycle. For this, the appropriate biases are provided by the VU. If the input current during stress and recovery lies inside the same current range, switching between them is very fast and the measurement delay is only determined by the bandwidth of the input amplifier, see Figure 9.18. However, different current ranges during stress and recovery require switching of the input stages of the TMI between different input gains. This adds an additional delay of at least \( \tsw =\SI {1}{\milli \second } \), which is quite short compared to general purpose instruments.

(image)

Figure 9.18:  (top) The switching transient between the stress and recovery is primarily defined by the bandwidth of the input buffer at different gains, see Figure 9.16. (bottom) If the input current ranges have to be switched, an additional delay of at least \( \tsw =\SI {1}{\milli \second } \) is introduced because mechanical relays are used to select the gain of the I/V converter unit. The typical bouncing characteristics occurring when the switch position of a relay is changed is visible during the switching cycle (colored light gray).

Furthermore, the DAU provides two measurement and two sampling modes, leading to four possible sampling configurations, summarized in Table 9.4.

\( \fsmax \) uniform sampling non-uniform sampling switch gain
\( \SI {14}{\bit } \) fast mode 1 MHz Yes Yes No
\( \SI {14}{\bit } \) normal mode 250 kHz Yes Yes Yes
\( \SI {16}{\bit } \) fast mode 750 kHz Yes Yes No
\( \SI {16}{\bit } \) normal mode 250 kHz Yes Yes Yes

Table 9.4:  The available configurations of the DAU are summarized in the table above. It has to be noted, that the same measurement resolution is achieved for the \( \SI {14}{\bit } \) and \( \SI {16}{\bit } \) mode. However, the input current ranges of the \( \SI {16}{\bit } \) mode are two times the input current ranges of the \( \SI {14}{\bit } \) mode.

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