Experimental Characterization of Bias Temperature Instabilities in Modern Transistor Technologies

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12.2 Single Charge Trapping

To get a detail insight into the charge trapping kinetics, single defects have to be studied. This can be achieved using nanoscale devices by employing the TDDS. In the following, the results of single defect characterization using the scaled SiGe devices with different Si cap layer thicknesses and the reference devices are discussed. First, the recovery traces and the complementary cumulative distribution functions (CCDFs) of the step heights of the three device variants are compared. Next, the charge transition times of various single defects are extracted and finally modeled using our four-state NMP model.

12.2.1 Characterization of Single Defects

To experimentally characterize a single defect, its intricate bias and temperature dependent capture and emission times have to be determined. In combination with the step height, that is the threshold voltage shift caused by this single defect, the transition times are more or less unique fingerprints of each single defect. To measure the single defect characteristics the TDDS is used in combination with our developed TMI, see Section 8 and Section 9. Using our equipment, the nanoscale SiGe devices with different Si cap layer thicknesses and the reference devices are repeatedly stressed at constant gate voltages varied between $\VGStress \in [\SI {-0.7}{\volt },\SI {-2.6}{\volt }]$ during which the drain-source voltage is $\VDStress =\SI {0}{\volt }$ to prevent HCD related effects. After each stress cycle a recovery gate voltage in the range of $\VGRead \in [\SI {0.1}{\volt },\SI {-0.5}{\volt }]$ is applied and the drain-source current is recorded at a drain bias of $\VDRead =\SI {-100}{\milli \volt }$ .

The initial recovery traces are shown in Figure 12.6 for all three device variants and reveal that a large number of discrete (math image) steps are present.

Each (math image) step corresponds to a single defect which has been charged during the stress cycle and uncharges during the recovery cycle. Although all three DUTs nominally have the same gate stack, the number of steps in the recovery traces differs significantly in all three devices. In particular, for the same stress voltage the devices with the thickest Si cap have the largest number of active defects, followed by the Si reference device. The smallest number of active defects is observed in the SiGe device with the thinnest Si cap. As can be seen, at the end of the measured recovery traces a significant threshold voltage shift (math image) remains. This is due to defects which have been charged during the stress cycle but have not emitted their charge during the recovery cycle. A further increase of the measurement window, that is the recovery time, would lead to a lower remaining . It has to be noted that single defects can have emission times up to weeks, month or even years [MWC19]. Following from that, a negligible remaining (math image) would require ultra long recovery times.

Considering the $\IDVG$ characteristics, in Figure 12.1 (right), all three technologies have different threshold voltages. Using (12.1), apparently the device with the thinnest Si cap is subjected to the largest overdrive, however, it still degraded less than all the others. Thus, the difference in the threshold voltages does not explain the observed difference in the device threshold voltage shift.

To study the distribution of the step heights, the complementary cumulative distribution functions (CCDFs) of the step heights $d$ of the hole traps present in more than 680 nanoscale transistors of all device variants is shown in Figure 12.7 (left). The mentioned active trap density (math image) and average step height of a single defect $\eta$ is extracted using ((8.9)) and ((8.10)) for both the unimodal and the bimodal CCDF, respectively.

As can be seen from the CCDFs, the step heights of the transistors with (math image) and the reference transistors appear to be unimodally distributed. However, the devices with have a significantly lower mean number of defects, $\NT =6.24$ , compared to the reference transistor with $\NT =36.85$ . A particularly noteworthy observation is that the step heights for the devices with the thick Si cap layer follow a bimodal distribution. Furthermore, the unimodally distributed CCDF of the (math image) devices and the first part of the bimodal CCDF of the transistors with can both be fitted with $\eta =2.14$ . The second part of the bimodal CCDF shows a significantly larger value for $\eta$ , indicating that the defects are closer to the channel than is the case for smaller $\eta$ .

The unimodal CCDFs appear to be a consequence of the dominant conduction channel present at the SiCap/ $\SiGe$ interface and the channel at the $\SIO$ /SiCap interface for the device with the thinnest Si cap layer and the reference Si devices, respectively. For a bimodal CCDF the defects appear to interact with two conducting channels. Furthermore, in nanoscale devices the position of random discrete dopands within the channel influences the percolation path of the drain-source current. It is conceivable that the dopands within the Si cap are unfavorably located in a way that only a single current path either in the SiGe layer or at the $\SIO$ /SiCap interface is present whereas the other channel is turned off. Moreover, it is possible that defects located near the $\SIO$ /SiCap interface can influence the potential of both channels, leading to very large step heights. From that it follows that there is no unique relation between the step height of a single defect and the corresponding channel the single defect is interacting with. However, the CCDF is created from a large number of defects (more than 4000 for the devices with the thick Si cap layer) and devices. Based on the $\eta$ values observed from our experimental data for the devices with the thick Si cap layer we link the first part of the bimodal CCDF to charge trapping interaction with a channel present in the SiGe layer and the tail of the distribution to a superposition of charge trapping interactions between the gate stack and the SiGe and/or $\SIO$ /SiCap channel.

The average $\dVth$ of the single traces used to calculate the CCDF is shown in Figure 12.7 (right). In accordance with the CCDF, the devices with the thinnest Si cap layer show the smallest threshold voltage shift whereas an approximately ten times higher average threshold voltage shift is observed for the reference devices. This trend reflects the decreased NBTI present in the SiGe devices with respect to the reference devices.

At that point it has to be noted that the recovery is very sensitive to the readout/recovery bias conditions. To ensure that the recovery traces are recorded at comparable bias conditions, a current criterion is used to determine the recovery voltage. As shown in the (math image) characteristics in Figure 12.1, the recovery voltage is set to $\VGRead =\VG (\IDS =\SI {-1}{\micro \ampere })$ . According to (12.1) a comparable oxide field is then applied to all DUTs during recovery. Using the current criterion the recovery traces used for the computation of the CCDF are recorded.

Using the experimental recovery traces from Figure 12.7 (right) the evaluation of the threshold voltage shift of 100 devices for the three device variants at certain recovery times is shown in Figure 12.8.

The standard deviation of the (math image) distribution is found to decreases for larger recovery times. Quite remarkably, a correlation between the standard deviation $\sigma$ and the maximum observed step height for a device variant is visible. The larger the largest observed step is, see Figure 12.7 (left), the larger $\sigma$ is. This is also the case for the standard deviations from the (math image) distributions analyzed at certain recovery times.

Next, the discrete (math image) steps from the recovery traces of various SiGe transistors are extracted and binned into spectral maps, see Section 8.1.

In such spectral maps the single defects are represented by clusters. From our SiGe MOSFETs, eight defects have been identified in the device variant with (math image) and the reference transistors and seven defects are studied in more detail in the devices with . Considering the spectral maps, the temperature dependence of charge emission of all defects can be seen very well. When the device temperature is increased, the clusters move towards shorter emission times confirming the temperature activation of charge transitions. To determine the thermal activation energies of charge capture and emission, the transition time characteristics of the single defects are recorded at different temperatures. Afterwards, the time dependence can be described by an Arrhenius' Law, see Section 8.3. The activation energies of 23 single defects are shown in Figure 12.10.

A broad distribution of activation energies for charge capture and emission is found.

12.2.2 Modeling of Single-Defects

By probing the nanoscale SiGe devices over several month the capture and emission time characteristics and the bias and temperature dependence of various single defects has been extracted. Among these single defects, bias independent emission times, which are typically referred to as fixed oxide traps, and switching traps with bias dependent emission times are found, see Figure 12.11.

Conversely, the capture time of the fixed and switching trap strongly depends on the NBTI stress bias. An increase of the device temperature affects both, the capture and emission time, and leads to shorter charge transition times.

To explain the bias and temperature dependent transition times, the four-state NMP model is used, see Section 7.3.3. The NMP transition rates are thereby calculated using our classical device Minimos-NT, and the initially calibrated device structure. Using our simulation framework the defect parameters of the four-state NMP model are adjusted to reproduce the experimental capture and emission times of the single defects. As can be seen in Figure 12.11, the four-state NMP model explains the capture and emission time characteristics of the fixed oxide traps and switching traps very well. Note that in the particular context of our SiGe devices it was found to be of utmost importance that the four-state NMP model not only considers the charge exchange with the conducting channel but also with the metal-gate as recently demonstrated for very thin oxides [183].

When transition time characteristics of single defects are investigated using the four-state NMP model, the bias dependence of the capture time plays an important role because in the four-state NMP model it is determined by the trap depth, see Section 7.3.3. According to the NMP model, the charge capture time is given by

$(12.4) \begin{equation} \tauc = \tau _{12’} + \tau _{2’2}\left (1+\frac {\tau _{\mathrm {12’}}}{\tau _{2’1}}\right ) \end{equation}$

with $\tau _{\mathrm {ij}}$ the first passage times between the individual states [173]. Considering the transitions $1\rightarrow 2’$ and $2’\rightarrow 1$ as NMP barriers and the transition $2’\rightarrow 2$ as a thermal barrier, the capture time dependence on the stress bias is

$(12.5) \begin{equation} \frac {\partial \tauc }{\partial \VGStress } = -\beta q \underbrace {\frac {\partial \phi (x, \VGStress )}{\partial \VGStress }}_{\phi ’(x)} \left (\frac {1}{2}\tau _{12’} + \tau _{2’2}\frac {\tau _{\mathrm {12’}}}{\tau _{2’1}}\right ) \end{equation}$

with $\beta =1/(\kB T)$ and $\phi (x, \VGStress )$ the potential inside the gate stack. For the employed gate stack we get

$\phi ’(x) = \begin {cases} x \leq \dSiO & 1/(1+\alpha ^{-1}) \times x/\dSiO \\ x > \dSiO & 1/(1+\alpha ^{-1}) + \\ & \hspace *{2mm}1/(1+\alpha )\times (x-\dSiO )/\dHfO \end {cases}$

with $\alpha =(\dHfO /\dSiO )(\epsSiO /\epsHfO )$ , whereas $x=0$ is at the IL/SiCap interface. The farther the defect is away from the IL/SiCap interface the larger $\phi ’(x)$ becomes and $\partial \tauc /\partial \VGStress$ increases. Thus for a strong bias dependence of the capture time the defect must be located more closely to the MG, and in case of a weaker bias dependence the defect resides near the Si cap layer. As can be seen in Figure 12.12, among all device variants no correlation between the bias dependence of the capture time and the Si cap layer thickness has been found and thus a similar trap depth distribution among the device variants must be present.