13.2 Results of Voltage Sweep Technique

Next, the impact of stress/recovery time and gate bias range of the sweeps on the permanent is studied using large-area transistors. Afterwards, the proposed method is applied to nanoscale pMOSFETs.

13.2.1 Large-Area Transistors

As mentioned before, whether a defect contributes to or not depends on whether its transition times are “small” or “large”. Considering a pMOSFET used in complex circuits with cycled on and off times, the question arises how the stress and recovery times impact . Figure 13.4 shows the behavior of extracted from our measurements performed with different duty cycles of on a large-area pMOSFET ().

As can be seen, the measured appears to be independent of the duty cycle of the selected stress and recovery times. This trend would not be visible if only recovery traces are used to study , as the full threshold voltage shift strongly depends on the stress and recovery time. In contrast, a notable impact on is observed at different gate voltage ranges used for the measurement, see Figure 13.5.

The more the gate bias is increased, that means. the more the pMOSFET operates in depletion and accumulation, the smaller gets. This is a consequence of the large amount of charge which is removed during accumulation.

13.2.2 Nanoscale Transistors

In agreement to TDDS investigations using nanoscale transistors, discrete charge capture and emission events are clearly visible in the sweeps. These discrete steps allow a clear identification of single defects, see Figure 13.6.

Among the studied defects various types where found consistent with fixed oxide traps and switching traps. Due to our experimental limit the lowest accessible trap level was approximately below the Fermi-level. However, interface states are located around . Thus no interface state could not be clearly detected. To overcome this limitation, the current measurement resolution of the TMI is enhanced for further investigations.