D I S S E R T A T I O N

Integrated Semiconductor Technology Analysis

ausgeführt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften
eingereicht an der Technischen Universität Wien
Fakultät für Elektrotechnik

von

Christoph Pichler

Rasumofskygasse 32
Wien III.
Matrikelnummer 8404337
geboren am 4. Februar 1966 in Wien

Wien, im März 1997

 
• Kurzfassung
• Abstract
• Acknowledgment
• List of Figures
• List of Tables
• 1 Introduction
  • 1.1 Semiconductor Technology
    • 1.1.1 ECAD: Electronic Computer Aided Design
    • 1.1.2 CIM: Computer Integrated Manufacturing
    • 1.1.3 TCAD: Technology Computer Aided Design
  • 1.2 VISTA/SFC TCAD Environment
    • 1.2.1 The VISTA Project
    • 1.2.2 Outline
• 2 TCAD Scenario
  • 2.1 TCAD Tasks
    • 2.1.1 Unit Process Analysis
    • 2.1.2 Device Analysis and Characterization
    • 2.1.3 Interconnect Simulation
    • 2.1.4 Circuit Simulation
    • 2.1.5 Process Tuning
    • 2.1.6 Calibration
      • Tool Calibration
      • Global Calibration
      • Experimental Data
    • 2.1.7 Sensitivity Analysis
    • 2.1.8 Design Centering and Yield Optimization
    • 2.1.9 Device Matching
    • 2.1.10 Technology Development and Evaluation
    • 2.1.11 Process Synthesis
    • 2.1.12 Inverse Modeling
  • 2.2 TCAD Tools
    • 2.2.1 Point Simulators
    • 2.2.2 Multistep Simulators
    • 2.2.3 Response Surface Models
    • 2.2.4 TCAD Frameworks and Virtual Fabs
• 3 The VISTA/SFC TCAD Environment
  • 3.1 VISTA/SFC Introduction
  • 3.2 Objectives
    • 3.2.1 Simulation Tool Integration
    • 3.2.2 Experiment Management
    • 3.2.3 Task Automation
  • 3.3 Architecture and Components
    • 3.3.1 Task Control Layer
    • 3.3.2 Simulation Flow Control
    • 3.3.3 Tool Binding
  • 3.4 VISTA/SFC and the VISTA Framework
    • 3.4.1 VISTA/SFC Graphical User Interface
  • 3.5 Concurrent Clients
    • 3.5.1 Encapsulation of External Clients
  • 3.6 Implementation of VISTA/SFC
• 4 Integration of Simulation Tools
  • 4.1 Heterogeneous Process Simulation Tools
    • 4.1.1 Tool Specialization
    • 4.1.2 Tool Categories
    • 4.1.3 Tools and Tool Applications
  • 4.2 Tool Integration
  • 4.3 Data Level
    • 4.3.1 PIF: Profile Interchange Format
    • 4.3.2 Native Tool Formats
    • 4.3.3 Consistent Wafer Representation
    • 4.3.4 Gridding
  • 4.4 Control Level
    • 4.4.1 Binding Function
    • 4.4.2 Tool Resources
    • 4.4.3 Input Deck Templates
    • 4.4.4 Tool Description
  • 4.5 Simulator Calibration
  • 4.6 System Tool Interface
    • 4.6.1 Configuration
    • 4.6.2 UNIX Networking
• 5 Semiconductor Process Flow Representation
  • 5.1 Fabrication Process Steps
  • 5.2 Process Simulation Tools
  • 5.3 Operations, Steps, and Flows
  • 5.4 Process Flow Representations
    • 5.4.1 PFR for Manufacturing
    • 5.4.2 Simulator Input Languages
  • 5.5 The VISTA/SFC Process Flow Representation
  • 5.6 Equipment, Processes, and Simulators
    • 5.6.1 Mapping
  • 5.7 Structure
    • 5.7.1 Steps
    • 5.7.2 Operations
    • 5.7.3 Modules
    • 5.7.4 Libraries
    • 5.7.5 Data Flow
    • 5.7.6 Variational Flows
  • 5.8 Statements
  • 5.9 Programming Interface
    • 5.9.1 File Format
  • 5.10 Graphical Flow Editor
  • 5.11 Layout Data
    • 5.11.1 Variational Masks
• 6 Run Control
  • 6.1 Projects
    • 6.1.1 Multiple Projects
  • 6.2 Experimental Splits
    • 6.2.1 Data Sharing Across Split Branches
  • 6.3 Incremental and Parallel Simulation
  • 6.4 Robust Operation and Error Handling
    • 6.4.1 Error Recovery
  • 6.5 Development and Debugging
    • 6.5.1 Process Development
    • 6.5.2 Single Step Operation
    • 6.5.3 Stop and Resume
    • 6.5.4 Rework
  • 6.6 Graphical User Interface
    • 6.6.1 Color Coding
    • 6.6.2 Managing Runs
    • 6.6.3 Viewing Output Data
  • 6.7 Text Terminal and Batch Mode Operation
    • 6.7.1 Why a GUI is not enough
    • 6.7.2 Text Terminal Operation
    • 6.7.3 Batch Mode Operation
• 7 Data Management
  • 7.1 Simulation Data
    • 7.1.1 Data Formats
      • Wafer Representation
    • 7.1.2 Data Files
    • 7.1.3 Tool Output Data
    • 7.1.4 Meta Data
    • 7.1.5 Persistence and Robustness
  • 7.2 Splitting and Data Dependency
• 8 Task Level TCAD Applications
  • 8.1 Design Parameterization and Variational Design
  • 8.2 Task Encapsulation
  • 8.3 EVE: Evaluable Entities
    • 8.3.1 Basic Functionality
    • 8.3.2 Nested Tasks
    • 8.3.3 Interface with Tool Agents
  • 8.4 EVE Classes
    • 8.4.1 Flow EVE
    • 8.4.2 RSM EVE
    • 8.4.3 RSM EVE Calibration
    • 8.4.4 Opt EVE
    • 8.4.5 LISP EVE
  • 8.5 EVI: Evaluation Instances
  • 8.6 Design of Experiments
  • 8.7 Response Surface Modeling
    • 8.7.1 System Linearization
  • 8.8 Optimization and Calibration
    • 8.8.1 Combining Tool and Calibrations
    • 8.8.2 Available Optimizers
  • 8.9 VISTA/SFC Programming Interface
  • 8.10 EVE: Graphical User Interface
• 9 Application Examples
  • 9.1 Standard CMOS Process
  • 9.2 Short Channel Effect Reduction with Pocket Implants
    • 9.2.1 Threshold Voltage Reduction
    • 9.2.2 Large Angle Tilt Implant Optimization
    • 9.2.3 Process Simulation
    • 9.2.4 Task Definition
    • 9.2.5 Optimization Result and Verification
  • 9.3 Summary
• 10 Discussion
  • 10.1 Benefits of TCAD Environments
  • 10.2 Side Effects on Simulators
  • 10.3 Implementation
  • 10.4 Development Process
  • 10.5 The Road Ahead
    • 10.5.1 Tool Integration and Task Abstraction
    • 10.5.2 Concurrent Design
    • 10.5.3 Version Control
    • 10.5.4 PIF Wafer Processor
    • 10.5.5 Internet Collaboration and WWW
• A LISP, XLISP, and VLISP
• B Callback Mechanism
• C Auxiliary PIF Tools
• References
• Publications
• Index
• About this document ...