D I S S E R T A T I O N

Rigorous TCAD Investigations on Semiconductor Fabrication Technology

ausgeführt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften

eingereicht an der Technischen Universität Wien
Fakultät für Elektrotechnik
von

Rudolf Strasser

Reindorfgasse 39/1
A-1150 Wien
Matrikelnummer 8925126
geboren am 22. Mai 1970 in Aurolzmünster

Wien, im Mai 1999

• Kurzfassung
• Abstract
• Acknowledgement
• Inhalt
• 1. Introduction
  • 1.1 The SIESTA TCAD Environment
  • 1.2 The Structure of this Work
• 2. Technology Computer Aided Design
  • 2.1 Process Modeling
    • 2.1.1 Topography Processing
      • 2.1.1.1 Lithography
      • 2.1.1.2 Etching and Deposition
    • 2.1.2 Ion Implantation
    • 2.1.3 Thermal Processing
      • 2.1.3.1 Rapid Thermal Annealing
      • 2.1.3.2 Oxidation
    • 2.1.4 Pseudo Process Models
  • 2.2 Electrical Modeling
    • 2.2.1 Device Simulation
    • 2.2.2 Interconnect Analysis
  • 2.3 Technology Characterization
    • 2.3.1 Statistical Analysis
  • 2.4 Process Optimization
    • 2.4.0.1 Performance
    • 2.4.0.2 Power Consumption
    • 2.4.0.3 Manufacturability
    • 2.4.0.4 Reliability
    • 2.4.1 Optimization Target
  • 2.5 Calibration of Models
• 3. Modeling Components
  • 3.1 Conventional TCAD
  • 3.2 The Historical Perspective
    • 3.2.1 The Data Level
      • 3.2.1.1 Wafer Representation
      • 3.2.1.2 Meshing Service
      • 3.2.1.3 Interpolation Service
      • 3.2.1.4 Data Interfaces
    • 3.2.2 Task Automation
  • 3.3 SIESTA's Modeling Approach
    • 3.3.1 Linear Sequences of Simulation Tools
    • 3.3.2 Simulation Networks
    • 3.3.3 Data Manipulation
    • 3.3.4 TCAD Models
      • 3.3.4.1 Data Ports
      • 3.3.4.2 The Description of Models
      • 3.3.4.3 Data Types
  • 3.4 The Simulation-Flow-Model
    • 3.4.1 The Simulation-Flow-Model's Description
    • 3.4.2 The Tool-Flow
      • 3.4.2.1 The Template Mechanism
      • 3.4.2.2 Symbol Values of Templates
      • 3.4.2.3 The Simulation Tool Interface
      • 3.4.2.4 Tool Invocation
    • 3.4.3 Mapping Tool Results to Output Ports
    • 3.4.4 Auxiliary Symbols
  • 3.5 The Network-Model
    • 3.5.1 Model Reuse
    • 3.5.2 Default Overloading
    • 3.5.3 The Network-Model's Description
      • 3.5.3.1 Input Ports of Submodels
      • 3.5.3.2 Output Ports of Submodels
  • 3.6 Auxiliary Models
    • 3.6.1 The Arithmetic-Model
    • 3.6.2 The Curve-Calculator-Model
    • 3.6.3 The Curve-To-File-Model
    • 3.6.4 The Curve-To-Vector-Model
    • 3.6.5 The Merge-Vector-Model
    • 3.6.6 The Copy-File-Model
• 4. SIESTA's TCAD Experiments
  • 4.1 The Generic Experiment
  • 4.2 Optimization Experiments
    • 4.2.1 Global Optimization
    • 4.2.2 A Levenberg-Marquardt Optimization Tool
    • 4.2.3 SIESTA's Process Optimization Environment
  • 4.3 Design of Experiments
  • 4.4 Statistical Analysis
• 5. Building Simulation Models
  • 5.1 Modeling Fabrication Processes
    • 5.1.1 Controlling Simulation Tools
    • 5.1.2 Capturing Simulation Results
    • 5.1.3 Using Results of Preceding Tools
    • 5.1.4 Lithography Masks
    • 5.1.5 Using Heterogeneous Process Simulation Tools
      • 5.1.5.1 Semiconductor Wafer Descriptions
  • 5.2 Performing Device Simulation
    • 5.2.1 Producing a Device Simulation Mesh
  • 5.3 Short Flow Methodologies
  • 5.4 Modeling Integrated Circuits
  • 5.5 Evaluation of Simulation-Flow-Models
    • 5.5.1 Split Checking
    • 5.5.2 Result Management
    • 5.5.3 Fault Tolerance
• 6. Parallel and Distributed Simulation
  • 6.1 Parallel Computation
    • 6.1.1 Bottom-Level Strategy
    • 6.1.2 Top-Level Strategy
    • 6.1.3 Summary
  • 6.2 Distributed Computing
    • 6.2.1 Workload Distribution
    • 6.2.2 Robustness
    • 6.2.3 Load Polling
      • 6.2.3.1 Estimation of the Effective System Load
    • 6.2.4 Host Selection
      • 6.2.4.1 Tool Management
      • 6.2.4.2 Host Validation and Ranking
  • 6.3 Performance Estimation
  • 6.4 User Interaction and Feedback
    • 6.4.1 The Queue Manager GUI
      • 6.4.1.1 Computation Hosts
      • 6.4.1.2 Job Queue
    • 6.4.2 Configuration of the Job Farming System
• 7. Implementation of SIESTA
  • 7.1 Implementation Issues
  • 7.2 The Modular Architecture
    • 7.2.1 Batch Operation
    • 7.2.2 Module Initialization and Termination
    • 7.2.3 Module Definition
      • 7.2.3.0.1 Required Modules.
      • 7.2.3.0.2 Source Files.
      • 7.2.3.0.3 Module Initialization.
      • 7.2.3.0.4 Module Termination.
      • 7.2.3.0.5 The Work Area.
      • 7.2.3.0.6 Menus.
  • 7.3 Persistent Storage of Objects
    • 7.3.1 Dynamical Instantiation
    • 7.3.2 Database of Persistent Objects
    • 7.3.3 Usage of Persistent Objects
  • 7.4 Graphical User Interface Modeling
    • 7.4.1 Component Abstraction and Reuse
    • 7.4.2 Interface Descriptions
    • 7.4.3 Maintenance Aspects
  • 7.5 The Job Farming Module
    • 7.5.1 Tasks
      • 7.5.1.1 Remote Execution
      • 7.5.1.2 Parallel Execution
      • 7.5.1.3 Communication Protocol
    • 7.5.2 Virtual Hosts
      • 7.5.2.1 Load polling
      • 7.5.2.2 Host State Detection
      • 7.5.2.3 Client Interface
    • 7.5.3 Load Balancing
  • 7.6 The Curve Module
    • 7.6.1 The Curve Viewer
• 8. Technology Optimization
  • 8.1 An Optimization Scenario
    • 8.1.1 Modeling the Fabrication Process
    • 8.1.2 Device Characterization
      • 8.1.2.1 Simulator Initialization
      • 8.1.2.2 Stability Enhancements
    • 8.1.3 Evaluation of the Quality Metric
    • 8.1.4 Configuring the Optimization Experiment
  • 8.2 Optimization Results
    • 8.2.1 Computation Efficiency
      • 8.2.1.1 Test Evaluation Phase
      • 8.2.1.2 Gradient Computation Phase
    • 8.2.2 System Scalability
• 9. Inverse Modeling with SIESTA
  • 9.1 A General Purpose Inverse Modeling Setup
    • 9.1.1 The TCAD Experiment
    • 9.1.2 Evaluation of a Model's Match
  • 9.2 Evolution of Simulation Models
  • 9.3 Inverse Modeling of Doping Profiles
    • 9.3.1 The Inverse Modeling Problem
    • 9.3.2 Modeling the Doping Profile
    • 9.3.3 Deriving a Metric for the Match
    • 9.3.4 Handling Multiple Devices and Bulk Biases
    • 9.3.5 Running the Inverse Modeling Procedure
    • 9.3.6 Simulation Results
• 10. Conclusion
  • 10.1 User Acceptance
  • 10.2 Robustness
  • 10.3 The Modular Implementation
  • 10.4 Further Research
    • 10.4.1 Analysis Capabilities
    • 10.4.2 Web Enabled TCAD
• A. The VLISP object system
  • A1. The Definition of a Class
• B. Notifications
• C. The CRV Data Format
• Literatur
• Curriculum Vitae
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