Contents

• 1. Introduction
• 2. Fundamentals of CMOS Devices
  • 2.1 Historical Overview
  • 2.2 Obstacles to Device Miniaturization
    • 2.2.1 Channel
    • 2.2.2 Gate Stack
    • 2.2.3 Source and Drain
    • 2.2.4 Gate Dielectric
  • 2.3 Novel Device Concepts
    • 2.3.1 Strained-Silicon Devices
    • 2.3.2 Depleted-Substrate Devices
    • 2.3.3 Vertical Transistors
    • 2.3.4 Carbon Nanotube FET
  • 2.4 Semiconductor Device Simulation
    • 2.4.1 Hierarchy of Semiconductor Device Simulation Models
    • 2.4.2 Classical Device Simulation
    • 2.4.3 Quantum Device Simulation
  
  
• 3. Tunneling in Semiconductors
  • 3.1 Tunneling Mechanisms
  • 3.2 The TSU-ESAKI Model
  • 3.3 Supply Function Modeling
    • 3.3.1 FERMI-DIRAC Distribution
    • 3.3.2 MAXWELL-BOLTZMANN Distribution
    • 3.3.3 Non-MAXWELLian Distributions
    • 3.3.4 Normalization
  • 3.4 The Energy Barrier
    • 3.4.1 The Metal-Oxide-Semiconductor Capacitor
    • 3.4.2 Image Force Correction
  • 3.5 Transmission Coefficient Modeling
    • 3.5.1 The WENTZEL-KRAMERS-BRILLOUIN Approximation
    • 3.5.2 The GUNDLACH Method
    • 3.5.3 Transfer-Matrix Method
    • 3.5.4 Quantum Transmitting Boundary Method
    • 3.5.5 Comparison
  • 3.6 Bound and Quasi-Bound States
    • 3.6.1 Eigenvalues of a Triangular Energy Well
    • 3.6.2 Eigenvalues of Arbitrary Energy Wells
    • 3.6.3 The Life Time of Quasi-Bound States
  • 3.7 Compact Tunneling Models
  • 3.8 Trap-Assisted Tunneling
    • 3.8.1 Model Overview
    • 3.8.2 The Model of JIMÉNEZ et al.
  • 3.9 Model Comparison
  
  
• 4. Implementation
  • 4.1 The Device Simulator MINIMOS-NT
  • 4.2 The Tunneling Model
    • 4.2.1 Single Segment Tunneling
    • 4.2.2 Stacked Segment Tunneling
    • 4.2.3 Trap-Assisted Tunneling
  • 4.3 The SCHRÖDINGER Solver
    • 4.3.1 Open and Closed Boundary conditions
    • 4.3.2 System HAMILTONian
    • 4.3.3 The Eigenvalue Solver
  
  
• 5. Applications
  • 5.1 Tunneling in MOS Transistors
    • 5.1.1 Tunneling Paths in MOS Transistors
    • 5.1.2 Channel Tunneling
    • 5.1.3 Source and Drain Extension Tunneling
    • 5.1.4 Hot-Carrier Tunneling in MOS Transistors
    • 5.1.5 Alternative Dielectrics for MOS Transistors
    • 5.1.6 Trap-Assisted Tunneling in ZrO Dielectrics
  • 5.2 Tunneling in Non-Volatile Memory Devices
    • 5.2.1 Conventional EEPROM Devices
    • 5.2.2 Alternative Non-Volatile Memory Devices
  
  
• 6. Summary and Conclusions
• A. The FOWLER-NORDHEIM Formula
  • A.1 Original FOWLER-NORDHEIM Formula
  • A.2 Correction for Direct Tunneling
  
  
• B. The WKB Approximation
• C. Wave Function Normalization for a Triangular Potential
• D. User Interface
  • D.1 Direct Tunneling
    • D.1.1 The Model FNPure
    • D.1.2 The Model FNLenzlingerSnow
    • D.1.3 The Model DTSchuegraf
    • D.1.4 The Model FrenkelPoole
    • D.1.5 The Model TsuEsaki
  • D.2 Stacked Segments
  • D.3 Oxide Traps
  • D.4 Trap-Assisted Tunneling
  
  
• Bibliography
• Own Publications

A. Gehring: Simulation of Tunneling in Semiconductor Devices